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"SiGe"

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"SiGe"

A Study of Dopant Distribution in SiGe Using Ion Implantation and Thermal Annealing
Won-chae Jung
J Electr Electron Mater 2018;31(6):377-385.   Published online September 1, 2018
For the investigation of dopant profiles in implanted Si1-xGex, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in Si1-xGex are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of Rp and 1.8% deviations of ΔRp owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of Rp and 8.1% deviations of ΔRp in the arsenic implanted Si0.2Ge0.8 layer and 8.5% deviations of Rp and 38% deviations of ΔRp in the Si0.5Ge0.5 layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the Si1-xGex layer becomes more important for accurate device scaling and fabrication technologies.
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Investigation of Strain Field on a Misfit Dislocation in a Strained Si Layer Using the CFTM Method
Wonjae Chang
J Electr Electron Mater 2017;30(12):757-761.   Published online December 1, 2017
The computational fourier-transform moire (CFTM) method has been briefly explained and this method was used to perform strain analysis of a misfit dislocation in a strained Si/Si0.55Ge0.45 layer. An essential advantage of the CFTM method is that it does not require unwrapping, such that errors due to improper unwrapping can be excluded. The analysis results revealed that the Si layer was grown with tensile stress on Si0.55Ge0.45 and lattice constant of the Si layer along the growth direction was 1.9% smaller than that of Si0.55Ge0.45. On the other hand, strain of the misfit dislocation in the strained Si/Si0.55Ge0.45 layer was maximum at the dislocation core due to an extra half-plane and the exx and eyy values were positive and negative, respectively, along the direction of a burgers vector.
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Thin Films and Sensors : The Study of Sputtered SiGe Thin Film Growth for Photo-detector Application
Do Young Kim, Sun Jo Kim, Hyung Jun Kim, Sang Youn Han, Jun Ho Song
J Electr Electron Mater 2012;25(6):439-444.   Published online June 1, 2012
For the application of photo-detector as active layer, we have studied how to deposit SiGe thin film using an independent Si target and Ge target, respectively. Both targets were synthesized by purity of 99.999%. Plasma generators were generated by radio frequency (rf, 13.56 MHz) and direct current (dc) power. When Ge and Si targets were sputtered by dc and rf power, respectively, we could observe the growth of highly crystalline Ge thin film at the temperature of 400℃ from the result of raman spectroscopy and X-ray diffraction method. However, SiGe thin film did not deposit above method. Inversely, we changed target position like that Ge and Si targets were sputtered by rf and dc power, respectively. Although Ge crystalline growth without Si target sputtering deteriorated considerably, the growth of SiGe thin film was observed with increase of Si dc power. SiGe thin film was evaluated as microcrystalline phase which included (111) and (220) plane by X-ray diffraction method.
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Electrical Properties of JFET using SiGe/Si/SiGe Channel Structure
B. G. Park, H. D. Yang, C. J. Choi, J. Y. Kim, K. H. Shim
J Electr Electron Mater 2009;22(11):905-909.   Published online November 1, 2009
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Comparison Study on Electrical Properties of SiGe JFET and Si JFET
B. G. Park, H. D. Yang, C. J. Choi, K. H. Shim
J Electr Electron Mater 2009;22(11):910-917.   Published online November 1, 2009
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Hole Mobility Characteristics of Biaxially Strained SiGe/Si Channel Structure with High Ge Content
J Electr Electron Mater 2008;21(1):44-48.   Published online January 1, 2008
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Electrical Properties of SiGe HBTs designed with Bottom Collector and Single Metal Layer Structures
J Electr Electron Mater 2007;20(8):661-665.   Published online August 1, 2007
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Comparison of Electrical Characteristics of SiGe pMOSFETs Formed on Bulk-Si and PD-SOI
J Electr Electron Mater 2007;20(6):491-495.   Published online June 1, 2007
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Low-frequency Noise Characteristics of Si0.8Ge0.2 pMOSFET Depending upon Channel Structures and Bias Conditions
J Electr Electron Mater 2006;19(1):1-6.   Published online January 1, 2006
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Effect of Ge Redistribution and Interdiffusion during Si(1-x)Gex Layer Dry Oxidation
J Electr Electron Mater 2005;18(12):1080-1086.   Published online December 1, 2005
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RBS Analysis on the Si0.9Ge0.1 Epitaxial Layer for the Fabrication of SiGe HBT
J Electr Electron Mater 2004;17(9):916-923.   Published online September 1, 2004
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Fabrication and characterization of the SiGe HBTs using an RPCVD
J Electr Electron Mater 2004;17(8):823-829.   Published online August 1, 2004
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High Quality Ultrathin Gate Oxides Grown by Low-Temperature Radical Induced Oxidation for High Performance SiGe Heterostructure CMOS Applications
Yeong Ju Song, Sang Hun Kim, Nae Eung Lee, Jin Yeong Kang, Gyu Hwan Sim
J Electr Electron Mater 2003;16(9):765-770.   Published online September 1, 2003
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Low-Temperature Selective Epitaxial Growth of SiGe using a Cyclic Process of Deposition-and-Etching
Sang Hun Kim, Seung Yun Lee, Chan U Park, Gyu Hwan Sim, Jin Yeong Kang
J Electr Electron Mater 2003;16(8):657-662.   Published online August 1, 2003
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Selective Epitaxial Growth of Si and SiGe using Si-Ge-H-Cl System for Self-Aligned HBT Applications
Sang Hoon Kim, Chan Woo Park, Seung Yun Lee, Kyu Hwan Shim, Jin Young Kang
J Electr Electron Mater 2003;16(7):573-578.   Published online July 1, 2003
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