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"Wafer"

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"Wafer"

Recent Development of P-Tunnel Oxide Passivated Contact Solar Cells
Yang Zhao, Muhammad Quddamah Khokhar, Hasnain Yousuf, Xinyi Fan, Seungyong Han, Youngkuk Kim, Suresh Kumar Dhungel, Junsin Yi
J Korean Inst Electr Electron Mater Eng 2023;36(4):332-340.   Published online July 1, 2023
DOI: https://doi.org/10.4313/JKEM.2023.36.4.3
Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.
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A Study on Characterization of P-N Junction Using Silicon Direct Bonding
Won-chae Jung
J Korean Inst Electr Electron Mater Eng 2017;30(10):615-624.   Published online October 1, 2017
DOI: https://doi.org/10.4313/JKEM.2017.30.10.615
This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.
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Wire Electric Discharge Machining Process of Various Crystalline Silicon Wafers
Hee-chan Moon, Sun-ho Choi, Sung-hee Park, Bo-yun Jang, Jun-soo Kim, Moon-hee Han
J Korean Inst Electr Electron Mater Eng 2017;30(5):301-306.   Published online May 1, 2017
DOI: https://doi.org/10.4313/JKEM.2017.30.5.301
Wire electrical discharge machining (WEDM) process was evaluated to slice Silicon (Si) for various applications. Specifically, various Si workpieces with various resistances, such as single and multi crystalline Si bricks and wafers were used. As conventional slicing processes, such as slurry-on or diamond-on wire slicing, are based on mechanical abrasions between Si and abrasive, there is a limitation to decrease the wafer thickness as well as kerf-loss. Especially, when the wafer thickness is less than 150 μm, wafer breakage increases dramatically during the slicing process. Single crystalline P-type Si bricks and wafers were successively sliced with considerable slicing speed regardless of its growth direction. Also, typical defects, such as microcracks, craters, microholes, and debris, were introduced when Si was sliced by electrical discharge. Also, it was found that defect type is also dependent on resistance of Si. Consequently, this study confirmed the feasibility of slicing single crystalline Si by WEDM.
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Regular Paper : Improving Efficiency of Low Cost EFG Ribbon Silicon Solar Cells by Using a SOD Method
Byeong Guk Kim, Jong Youb Lim, Hao Chu, Byoung Jin Oh, Jae Hwan Park, Jin Seok Lee, Bo Yun Jang, Young Soo An, Dong Gun Lim
J Korean Inst Electr Electron Mater Eng 2011;24(3):240-244.   Published online March 1, 2011
DOI: https://doi.org/10.4313/JKEM.2011.24.3.240
The high cost of crystalline silicon solar cells has been considered as one of the major obstacles to their terrestrial applications. Spin on doping (SOD) is presented as a useful process for the manufacturing of low cost solar cells. Phosphorus (P509) was used as an n-type emitters of solar cells. N-type emitters were formed on p-type EFG ribbon Si wafers by using a SOD at different spin speed (1,000∼4,000 rpm), diffusion temperatures (800℃∼950℃), and diffusion time (5∼30 min) in N2+O2 atmosphere. With optimum condition, we were able to achieve cell efficiency of 14.1%.

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  • SiC Contaminations in Polycrystalline-Silicon Wafer Directly Grown from Si Melt for Photovoltaic Applications
    Ye-Neung Lee, Bo-Yun Jang, Jin-Seok Lee, Joon-Soo Kim, Young-Soo Ahn, Woo-Young Yoon
    Journal of the Korea Foundry Society.2013; 33(2): 69.     CrossRef
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Effect of Pad Thickness on Removal Rate and Within Wafer Non-Uniformity in Oxide CMP
Jae Hyun Bae, Hyun Seop Lee, Jae Hong Park, Hideaki Nishizawa, Masaharu Kinoshita, Hae Do Jeong
J Korean Inst Electr Electron Mater Eng 2010;23(5):358-363.   Published online May 1, 2010
DOI: https://doi.org/10.4313/JKEM.2010.23.5.358

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  • Effects of CMP Retaining Ring Material on the Performance of Wafer Polishing
    Ki-Won Park, Eun-young Kim, Dong-Sam Park
    Journal of the Korean Society of Manufacturing Process Engineers.2020; 19(3): 22.     CrossRef
  • Effects of Insert Materials of Retaining Ring on Polishing Finish in Oxide CMP
    Ki-Won Park, Dong-Sam Park
    Journal of the Korean Society of Manufacturing Process Engineers.2019; 18(8): 44.     CrossRef
  • Finite Element Analysis on Dynamic Viscoelasticity of CMP Polishing Pad
    Byeongjun Pak, Dasol Lee, Seonho Jeong, Hyunjin Kim, Haedo Jeong
    Journal of the Korean Society for Precision Engineering.2019; 36(2): 177.     CrossRef
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Development and Characterization of Vertical Type Probe Card for High Density Probing Test
J Korean Inst Electr Electron Mater Eng 2006;19(9):825-831.   Published online September 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.9.825

Citations

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  • Probe card-Type multizone electrostatic chuck inspection system
    Yoon Sung Koo, Jae Hwan Kim, Chan Su Han, Sang Jeen Hong
    Automatika.2023; 64(2): 389.     CrossRef
  • Optimization of Thermal Deformation in Probe Card
    Yong-Hoon Chang, Jeong-Je Yin, Yong-S. Suh
    Journal of the Korea Academia-Industrial cooperation Society.2010; 11(11): 4121.     CrossRef
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Effect of Pad Surface Characteristics on Within Wafer Non-uniformity in CMP
J Korean Inst Electr Electron Mater Eng 2006;19(4):309-313.   Published online April 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.4.309
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A Study on the Within Wafer Non-uniformity of Oxide Film in CMP
J Korean Inst Electr Electron Mater Eng 2005;18(6):521-526.   Published online June 1, 2005
DOI: https://doi.org/10.4313/JKEM.2005.18.6.521
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Crystalline Properties of Carbon Nitride Films According to Substrates and Growth Conditions
Ji Gong Lee, Seong Pil Lee
J Korean Inst Electr Electron Mater Eng 2003;16(12):1103-1109.   Published online December 1, 2003
DOI: https://doi.org/10.4313/JKEM.2003.16.12.1103
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Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method
O Seong Song, Gi Yeong Lee
J Korean Inst Electr Electron Mater Eng 2003;16(10):859-864.   Published online October 1, 2003
DOI: https://doi.org/10.4313/JKEM.2003.16.10.859
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Bonding Property of Silicon Wafer Pairs with Annealing Method
Hong Seok Min, Sang Hyun Lee, Oh Sung Song, Young Chang Joo
J Korean Inst Electr Electron Mater Eng 2003;16(5):365-371.   Published online May 1, 2003
DOI: https://doi.org/10.4313/JKEM.2003.16.5.365
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Single Crystal Silicon Thin Film Transistor using SOI Wafer for the Switching Device of Top Emission Type AMOLEDs
Jae Won Chang, Hoon Kim, Kyeong Sik Shin, Jai Kyeong Kim, Byeong Kwon Ju
J Korean Inst Electr Electron Mater Eng 2003;16(4):292-297.   Published online April 1, 2003
DOI: https://doi.org/10.4313/JKEM.2003.16.4.292
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Wafer Level Packaging of RF-MEMS Devices with Vertical Feed-through
Yong Gug Kim, Yun Gwon Park, Jae Gyeong Kim, Byeong Gwon Ju
J Korean Inst Electr Electron Mater Eng 2003;16(12s):1237-1241.
DOI: https://doi.org/10.4313/JKEM.2003.16.12s.1237
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Design and Fabrication of Film Bulk Acoustic Resonator for Flexible Microsystems
Yu Li Kang, Yong Gug Kim, Su Won Kim, Byeong Gwon Ju
J Korean Inst Electr Electron Mater Eng 2003;16(12s):1224-1231.
DOI: https://doi.org/10.4313/JKEM.2003.16.12s.1224
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