In parallel with the efforts to improve the device performance in modern integrated circuits, it is necessary to downscale their core components, field-effect transistors (FETs), generally gauged by their physical gate length. Upon such device scaling, the emergence of the short-channel effect impedes further scaling into the nanometer scale in the silicon VLSI (Very-Large-Scale-Integration) system. To address this issue, two-dimensional (2D) semiconductors, leveraging their atomically thin thickness and dangling-bond-free characteristics, are being highlighted as a material solution for future scaling technology without severe mobility degradation. Despite the expected ideal physical properties, 2D semiconductors have yet to realize their full potential owing to the limited development of integration technology. In this context, we survey and review the tailored van der Waals integration technologies for 2D FETs. In particular, we provide an in-depth study of both van der Waals integrated contact and dielectric methods along with an explanation of customized materials. In essence, this van der Waals integrationcentered approach will be a core strategy to implement the high-performance 2D transistors that meet the demand of FET miniaturization.

As a potential alternative to flash memory, HfO₂/Al₂O₃ stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO₂/Al₂O₃ stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO₂ layer, the memory window of the 5-layered stack increased by 152.4% after O₂ annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO₂/Al₂O₃ stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O₂ and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

Non-volatile memory is approaching its fundamental limits with the Si3N4 storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

IZO transistors with Al₂O₃ as gate dielectrics have been investigated. To improve permittivity in an ambient dielectric layer, we grew Al₂O₃ by atomic layer deposition directly onto the substrates. Then, we prepared IZO semiconductor solutions with 0.1 M indium nitrate hydrate [In(NO₃)₃·xH₂O] and 0.1 M zinc acetate dehydrate [Zn(CH₃COO)₂·2H₂O] as precursor solutions; the IZO solution made with a molar ratio of 7:3 was then prepared. It has been found that these oxide transistors exhibit low operating voltage, good turn-on voltage, and an average field-effect mobility of 0.90 ㎠/Vs in ambient conditions. Studies of low-voltage driving of IZO transistors with atomic layer-deposited high-k Al₂O₃ as gate dielectric provide data of relevance for the potential use of these materials and this technology in transparent display devices and displays.

We fabricated the electrolyte-insulator-semiconductor (EIS) devices with various high-k sensing membranes to realize a high quality pH sensor. The sensing properties of each high-k dielectric material were compared with those of conventional SiO2 (O) and SiO2/Si3N4 (ON) membranes. As a result, the high-k sensing membranes demonstrated better sensitivity and stability than the O and ON membranes. Especially, the SiO2/HfO2 (OH) stacked layer showed a high sensitivity and the SiO2/Al2O3 (OA) stacked layer exhibited an excellent chemical stability. In conclusion, the high-k sensing membranes are expected to have excellent operating characteristics in terms of sensitivity and chemical stability for the biosensor application.

In this paper, matching characteristic of MIM (metal-insulator-metal) capacitor with Al2O3/HfO2/Al2O3 (AHA) structure is analyzed. The floating gate capacitance measurement technique (FGMT) was used for analysis of matching characteristic of the MIM capacitors in depth. It was shown that matching coefficient of AHA MIM capacitor is 0.331%㎛ which is appropriate for application to analog/RF integrated circuits. It was also shown that the matching coefficient has a more strong dependence on the width than length of MIM capacitor.

In this paper, reliability of the two sandwiched MIM capacitors of Al2O3-HfO2-Al2O3 (AHA) and SiO2-HfO2-SiO2 (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/μm2 and 5.2 fF/μm2) over the entire frequency range and low leakage current density of ∼1 nA/cm2 at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (ΔC/C0) increases and the variation of voltage linearity (α/α0) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

We investigated the effects of low temperature (500℃) O2 annealing on the characteristics of hafnium silicate (HfSi(x)O(y)) films deposited on a Si substrate by atomic layer deposition (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics such as flat band voltage shift (ΔV(fb)) by hysteresis without oxide capacitance reduction. We suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of HfSi(x)O(y) films deposited by ALD.

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (ΔVT) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2∼3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

In this study, HfAlO3 thin films using gate insulator of MOSFET were etched in inductively coupled plasma. The etch characteristics of the HfAlO3 thin films has been investigated by varying O2/BCl3/Ar gas mixing ratio, a RF power, a DC bias voltage and a process pressure. As the O2 concentration increases further, HfAlO3 was redeposited. As increasing RF power and DC bias voltage, etch rates of the HfAlO3 thin films increased. Whereas, as decreasing of the process pressure, etch rates of the HfAlO3 thin films increased. The chemical reaction on the surface of the etched the HfAlO3 thin films was investigated with X-ray photoelectron spectroscopy (XPS). These peaks moved a binding energy. This chemical shift indicates that there are chemical reactions between the HfAlO3 thin films and radicals and the resulting etch by-products remain on the surface.