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"DMOSFET"

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"DMOSFET"

Design and Optimization of Doping Concentration of the JFET Region of 4H-SiC VDMOSFETs
Hye-won Lee, Ye-jin Kim, Chang-jun Park, Ji-soo Choi, Geon-hee Lee, Sang-mo Koo
J Korean Inst Electr Electron Mater Eng 2025;38(1):101-106.   Published online January 1, 2025
DOI: https://doi.org/10.4313/JKEM.2025.38.1.14
The 4H-SiC VDMOSFET demonstrates a high reverse breakdown voltage (BV) due to the JFET region but experiences relatively high on-resistance (Ron). A widely adopted method to reduce the Ron is to uniformly increase the doping concentration of the JFET region, which results in a trade-off that reduces the BV. This study proposes a method to optimize the segmentation of the JFET region by selectively increasing the doping concentration using ‘total doping’, ‘half-doping’, and ‘quarter-doping’. The optimized quarter segment with a specific doping concentration slightly reduces BV, but the sharp decrease in specific on-resistance (Ron,sp) results in a 105% improvement in the performance index, Baliga’s Figure of Merit (BFOM). This research suggests the potential for electrically superior designs by modifying the doping concentration in the JFET region of conventional VDMOSFET structures.
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The Electrical Properties of Post-Annealing in Neutron-Irradiated 4H-SiC MOSFETs
Taeseop Lee, Jae-in An, So-mang Kim, Sung-joon Park, Seulki Cho, Kee-nam Choo, Man-soon Cho, Sang-mo Koo
J Korean Inst Electr Electron Mater Eng 2018;31(4):198-202.   Published online May 1, 2018
DOI: https://doi.org/10.4313/JKEM.2018.31.4.198
In this work, we have investigated the effect of a 30-min thermal anneal at 550℃ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.
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Optimization of 4H-SiC DMOSFETs by Adjustment of the Dimensions and Level of the p-base Region
Jung Joon Ahn, Wook Bahng, Sang Chul Kim, Nam Kyun Kim, Hong Bae Jung, Sang Mo Koo
J Korean Inst Electr Electron Mater Eng 2010;23(7):513-516.   Published online July 1, 2010
DOI: https://doi.org/10.4313/JKEM.2010.23.7.513
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Effect of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs
Min Seok Kang, Kyoung Sook Moon, Sang Mo Koo
J Korean Inst Electr Electron Mater Eng 2010;23(6):436-439.   Published online June 1, 2010
DOI: https://doi.org/10.4313/JKEM.2010.23.6.436
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Mixed-mode Simulation of Switching Characteristics of Sic DMOSFETs
Min Seok Kang, Chang Yong Choi, Wook Bang, Sang Chul Kim, Nam Kyun Kim, Sang Mo Koo
J Korean Inst Electr Electron Mater Eng 2009;22(9):737-740.   Published online September 1, 2009
DOI: https://doi.org/10.4313/JKEM.2009.22.9.737
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A Simulation Study on the Structural Optimization of a 800 V 4H-SiC Power DMOSFET
Chang Yong Choi, Min Seok Kang, Wook Bahng, Sang Cheol Kim, Nam Kyun Kim, Sang Mo Koo
J Korean Inst Electr Electron Mater Eng 2009;22(8):637-640.   Published online August 1, 2009
DOI: https://doi.org/10.4313/JKEM.2009.22.8.637
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Study on the Electrical Characteristics of the Multi-RESURF SOI LDMOSFET as a Function of Epi-Layer Concentration
J Korean Inst Electr Electron Mater Eng 2006;19(9):813-817.   Published online September 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.9.813
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Breakdown Voltage and On-resistance Characteristics of the Surface Doped SOI RESURF LDMOSFET
J Korean Inst Electr Electron Mater Eng 2006;19(1):23-28.   Published online January 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.1.023
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Impacts of Process and Design Parameters on the Electrical Characteristics of High-Voltage DMOSFETs
J Korean Inst Electr Electron Mater Eng 2004;17(9):911-915.   Published online September 1, 2004
DOI: https://doi.org/10.4313/JKEM.2004.17.9.911
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A Study on the Formation of Trench Gate for High Power DMOSFET Applications
Hoon Soo Park, Jin Gun Koo, Young Ki Lee
J Korean Inst Electr Electron Mater Eng 2004;17(7):713-717.   Published online July 1, 2004
DOI: https://doi.org/10.4313/JKEM.2004.17.7.713
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Analysis of Electrical Characteristics of High-Density Trench Gate Power DMOSFET Utilizing Self-Align and Hydrogen Annealing Techniques
Hun Su Park, Jong Dae Kim, Sang Gi Kim, Yeong Gi Lee
J Korean Inst Electr Electron Mater Eng 2003;16(10):853-858.   Published online October 1, 2003
DOI: https://doi.org/10.4313/JKEM.2003.16.10.853
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