There is an increasing demand for freeform stretchable display technologies capable of overcoming spatial limitations in next-generation platforms such as augmented reality (AR) and virtual reality (VR). To realize such stretchable displays, all constituent materials—including semiconductors, electrodes, insulators, and substrates—must exhibit sufficient mechanical elasticity. To date, stretchable gate insulators have primarily relied on organic polymers such as poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA). However, their practical application is significantly limited by poor electrical properties, including low dielectric constant and instability. In this work, we propose a novel gate insulator structure that minimizes the use of solution-based processes, which often suffer from poor uniformity and may damage underlying layers during fabrication. The proposed structure integrates the advantages of both organic and inorganic materials by employing a hybrid configuration. Specifically, high-k HfO₂ thin films are deposited on both the top and bottom of an organic layer composed of PVP-co-PMMA, poly(melamine-co-formaldehyde) (PMF) as a crosslinking agent, and propylene glycol monomethyl ether acetate (PGMEA) as a solvent. This inorganic–organic–inorganic structure effectively compensates for the inherent electrical limitations of organic materials. As a result, the fabricated thin-film transistors (TFTs) exhibit improved electrical performance and reliability compared to devices employing a single organic gate insulator.

Neuromorphic computing, which mimics the energy-efficient parallel processing capabilities of the human brain, has emerged as an alternative to traditional von Neumann architectures that struggle with high power consumption in the era of artificial intelligence (AI). Despite the potential of Si-based neuromorphic chips, they often face fundamental limitations in integration density and biological compatibility, necessitating the development of next-generation devices that can better emulate the ionic signaling of biological systems. This review provides a comprehensive analysis of the recent research trends in artificial synapses and neurons based on organic electrochemical transistors (OECTs), highlighting their unique ability to achieve high transconductance and mixed ionic-electronic conduction at ultra-low operating voltages. We discuss how OECTs successfully replicate diverse synaptic plasticities and complex neuronal spiking behaviors through advanced material engineering and structural optimizations such as vertical architectures. Furthermore, this review discusses the implementation of high-order neural functions, including associative learning and logic operations, which are facilitated by the inherent electrochemical dynamics of organic semiconductors. Finally, overcoming current challenges in reliability and scalability will establish OECTs as a pivotal platform for low-power neuromorphic hardware and bio-integrated electronics.

With the advancement of the information society, the demand for highly integrated and multi-functional electronic devices is rapidly increasing. To meet these demands, high-performance transistors with low power consumption, high-speed operating, and mechanical flexibility are essential. Among various candidates, semiconducting single-walled carbon nanotubes (s-SWCNT)-based transistors, which exhibit intrinsically ambipolar characteristics, have emerged as promising components for CMOS-like circuits. In this study, s-SWCNT were selectively dispersed using rr-P3DDT, a thiophene-based conjugated polymer, and filed-effect transistors (FETs) were fabricated by inducting directional alignment for enhanced charge transport through an off-centered spin-coating process. The electrical characteristics of the fabricated s-SWCNT FETs were evaluated under various thermal annealing conditions (100℃, 150℃, 200℃, and 250℃). Off-centered spin-coated and high temperature annealed s- SWCNT FETs exhibited high field-effect mobilities over 5 cm²/Vs in both p-type and n-type operation, along with ideal Vshaped ambipolar transfer curves. These results indicate a significant enhancement in ambipolar performance due to efficient desorption of residual oxygen and water molecules in active channel via high temperature annealing. Furthermore, CMOS-like inverter circuits demonstrated an ideal inversion voltage (VIN = V_DD/2) and a high voltage gain of approximately 9.5. These findings highlight the potential of SWCNT-based materials for realizing next-generation flexible electronic circuits that combine high-performance, energy efficiency, and simplified solution-processing.

Neuromorphic computing, inspired by the biological mechanisms of neural signal transmission, has emerged as a promising technology for efficient and parallel data processing with minimal power consumption. In this study, we developed floating-gate organic thin-film transistors (OTFTs) with self-assembled monolayer (SAM)-based tunneling layers to mimic the characteristics of artificial synapses. The tunneling layers were formed using mixed phosphonic acid SAMs with varying ratios of octadecylphosphonic acid (ODPA) and 12-pentafluorophenoxydodecylphosphonic acid (PFPA). The influence of these ratios on the memory and neuromorphic characteristics of the devices was systematically evaluated. Our results revealed that the ODPA ratio significantly impacts the hysteresis window, with higher ODPA content yielding improved memory characteristics. Conversely, the PFPA : ODPA ratio of 2:1 exhibited the lowest non-linearity (NL = 0.48), demonstrating the potential for highly accurate weight updates in neuromorphic devices. Additionally, pulse width modulation studies showed that a pulse width of 100 ms optimized the linearity and stability of long-term potentiation (LTP) and depression (LTD) characteristics. The combination of sol-gel processed AlOx as a floating-gate layer and tailored SAM-based tunneling layers allowed for precise control of device performance. These findings highlight the importance of molecular engineering in designing SAM layers to balance memory retention and neuromorphic functionality. This study provides a pathway for advancing organic floating-gate transistors as a core component in next-generation neuromorphic computing systems.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

Underwater wireless communication is a challenging issue for realizing the smart aqua-farm and various marine activities for exploring the ocean and environmental monitoring. In comparison to acoustic and radio frequency technologies, the visible light communication is the most promising method to transmit data with a higher speed in complex underwater environments. To send data at a speedier rate, high-performance photodetectors are essentially required to receive blue and/or cyan-blue light that are transmitted from the light sources in a light-fidelity (Li-Fi) system. Here, we fabricated high-performance organic phototransistors (OPTs) based on P-type donor polymer (PTO2) and N-type acceptor small molecule (IT-4F) blend semiconductors. Bulk-heterojunction (BHJ) PTO2:IT-4F photo-active layer has a broad absorption spectrum in the range of 450~550 nm wavelength. Solution-processed OPTs showed a high photo-responsivity >1,000 mA/W, a large photo-sensitivity >10³, a fast response time, and reproducible light-On/Off switching characteristics even under a weak incident light. BHJ organic semiconductors absorbed photons and generated excitons, and efficiently dissociated to electron and hole carriers at the donor-acceptor interface. Printed and flexible OPTs can be widely used as Li-Fi receivers and image sensors for underwater communication and underwater internet of things (UIoTs).

In this work, the effect of sputtering working pressure for the tellurium film and its thin-film transistor was investigated. The transfer characteristics of tellurium thin-film transistors were improved by increasing the working pressure during sputtering process. As increasing working pressure, physical and optical properties of Te films such as crystallinity, transmittance, and surface roughness were improved. Therefore, the improved transfer characteristics of Te thin-film transistors may originate from both improved interface properties between the silicon oxide gate dielectric layer and the tellurium active layer with an improved quality of Te film. In conclusion, the control of working pressure during sputtering would be important for obtaining highperformance tellurium-based thin film transistor.

We investigated the effect of a post-annealing process using ultraviolet (UV) light on the electrical properties of solution-processed InZnO (IZO) thin-film transistors (TFTs). UV light was irradiated on IZO TFTs for different time periods of 0s, 30s, and 90s. We measured transfer and retention stability curves to evaluate the performance of the fabricated TFTs. In addition, we measured height, amplitude, and phase AFM images to analyze changes in the surface and morphology of the devices. AFM measurements were performed by setting the drive amplitude of the cantilever tip to 47.9 mV in tapping mode, then dividing the device surface into 500 nm × 500 nm. In the case of IZO TFT irradiated with UV for 30s, the electron mobility and Ion/Ioff ratio were improved, the threshold voltage was reduced by approximately 2 V, and the subthreshold swing also decreased form 1.34 V/dec to 1.11 V/dec.

Herein, we report the manufacture of high-performance, ambipolar organic field-effect transistors (OFETs) and complementary-like electronic circuitry based on a blended, polymeric, semiconducting film. Relatively high and wellbalanced electron and hole mobilities were achieved by incorporating a small amount of ionic additives. The equivalent P-channel and N-channel properties of the ambipolar OFETs enabled the manufacture of complementary-like inverter circuits with a near-ideal switching point, high gain, and good noise margins, via a simple blanket spin-coating process with no additional patterning of each active P-type and N-type semiconductor layer.

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electronwithdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

A soft baking process was used to enhance the electrical characteristics of solution-processed indium-zincoxide (IZO) thin-film transistors (TFTs). We demonstrate a stable soft baking process using a hot plate in air to maintain the electrical stability and improve the electrical performance of IZO TFTs. These oxide transistors exhibited good electrical performance; a field-effect mobility of 7.9 cm²/Vs, threshold voltage of 1.4 V, sub-threshold slope of 0.5 V/dec, and a current on/off ratio of 2.9×10⁷ were measured. To investigate the static response of our solutionprocessed IZO TFTs, simple resistor load type inverters were fabricated by connecting a resistor (5 or 10 MΩ). Our IZO TFTs, which were manufactured using the soft baking process at a baking temperature of 120℃, performed well at the operating voltage, and are therefore a good candidate for use in advanced logic circuits and transparent display backplanes.

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of 3.0(±0.2) cm²/Vs, high Ion/Ioff ratio of 1.1×10⁷, threshold voltage of 0.4(±0.1) V, and subthreshold swing of 0.7(±0.01) V/dec. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

IZO transistors with Al₂O₃ as gate dielectrics have been investigated. To improve permittivity in an ambient dielectric layer, we grew Al₂O₃ by atomic layer deposition directly onto the substrates. Then, we prepared IZO semiconductor solutions with 0.1 M indium nitrate hydrate [In(NO₃)₃·xH₂O] and 0.1 M zinc acetate dehydrate [Zn(CH₃COO)₂·2H₂O] as precursor solutions; the IZO solution made with a molar ratio of 7:3 was then prepared. It has been found that these oxide transistors exhibit low operating voltage, good turn-on voltage, and an average field-effect mobility of 0.90 ㎠/Vs in ambient conditions. Studies of low-voltage driving of IZO transistors with atomic layer-deposited high-k Al₂O₃ as gate dielectric provide data of relevance for the potential use of these materials and this technology in transparent display devices and displays.

In this study, we examine the electrical properties of diketopyrrolopyrrole (DPP) containing polymer semiconductors that have been reported to show high performance with ambipolar characteristics. We prepared three different DPP based polymer semiconductors (PDPPTPT, PDPP3T, and PDPP2T-TT) and fabricated organic thin film transistors (OTFTs) with ambipolar polymer semiconductors as an active layer. All three DPP polymers showed only p-type properties at initial measurements. However, after annealing in vacuum oven for 24 hours, it was found that the DPP based polymers have both p-type and n-type properties. It is speculated that the residual impurities supposedly regarded as a strong electron trap source were eliminated during the vacuum process.

In this study, the effects of soft baking temperature on the solution derived ZTO (Zn-Sn-O) TFTs (thin-film transistors) as a In-free oxide semiconductor were investigated. In spite of the same hard baking at high temperature(600℃), the electrical properties of ZTO TFT was greatly changed by a small difference in soft baking temperature(180~250℃). The performance of TFT was deteriorated as the soft baking temperature increased. Therefore, it is important to remove the water-related defects well as organic impurities from the ZTO films during soft baking for fabrication of solution-derived high performance of TFTs.

In this paper, TiO2 based thin-film transistors (TFTs) were fabricated using by an atomic layer deposition with high aspect ratio and excellent step coverage. Ti02 semiconducting layer was deposited showing a rutile phase through the rapid thermal annealing process, and exhibited TFT characteristics with a 200 pm channel length of low-leakage currents (none of current flow during off-state), stable threshold voltages (-10 V - 0 V), and a much higher on/off current ratio (