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"Planar"

Doping Optimization of 2.4 kV 4H-SiC Planar MOSFETs for Enhanced Electrical Performance
Taeyeong Yoon, Jeongmin Kim, Jun Lee, Songye Lim, Hyeondo Kang, Seung-hyun Park, Sang-mo Koo
J Electr Electron Mater 2025;38(6):672-676.   Published online November 1, 2025
DOI: https://doi.org/10.4313/JEEM.2025.38.6.10
Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 1017 to 6 × 1017 cm-3) and JFET regions (from 1 × 1016 to 7 × 1016 cm-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 1017 cm-3 and 5.3 × 1017 cm-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 1017 cm-3 and 1.5 × 1016 cm-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm2 and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 1017 cm-3 and 5.0 × 1016 cm-3, the Ron,sp was reduced to 1.31 mΩ·cm2 while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.
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Enhancement of SiO2 Uniformity by High-Pressure Deuterium Annealing
Yong-sik Kim, Dae-han Jung, Hyo-jun Park, Ju-won Yeon, Tae-hyun Kil, Jun-young Park
J Korean Inst Electr Electron Mater Eng 2024;37(2):148-153.   Published online March 1, 2024
DOI: https://doi.org/10.4313/JKEM.2024.37.2.4
As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher chip density, thin-film layers have been deposited iteratively. The poor film uniformity resulting from deposition or chemical mechanical planarization (CMP) significantly affects chip yield. Therefore, the development of novel fabrication processes to enhance film uniformity is required. In this context, high-pressure deuterium annealing (HPDA) is proposed to reduce the surface roughness resulting from the CMP. The HPDA is carried out in a diluted deuterium atmosphere to achieve cost-effectiveness while maintaining high pressure. To confirm the effectiveness of HPDA, time-of-flight secondary-ion mass spectrometry (ToF-SIMS) and atomic force microscopy (AFM) are employed. It is confirmed that the absorbed deuterium gas facilitates the diffusion of silicon atoms, thereby reducing surface roughness.

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  • Analysis of Yield and Electrical Characteristics of Ag Electrode-Based Volatile Threshold Switching Memristors with Al2O3 Dielectric Films Under Different ALD Process Conditions
    Wan-Sik Woo, Seung-Jin Lee, Moon-Seok Kim, Seung-Bae Jeon
    Journal of Electrical and Electronic Materials.2026; 39(5): 493.     CrossRef
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Analysis of Electrical Characteristics According to the Pillar Spacing of 4.5 kV Super Junction IGBT
Geon Hee Lee, Byoung Sup Ahn, Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2020;33(3):173-176.   Published online May 1, 2020
DOI: https://doi.org/10.4313/JKEM.2021.33.3.3
This study focuses on a pillar in which is implanted a P-type maneuver under a P base. This structure is called a super junction structure. By inserting the pillar, the electric field concentrated on the P base is shared by the pillar, so the columns can be dispersed while maintaining a high breakdown voltage. Ten pillars were generated during the multi epitaxial process. The interval between pillars is varied to optimize the electric field to be concentrated on the pillar at a threshold voltage of 6 V, a yield voltage of 4,500 V, and an on-state voltage drop of 3.8 V. The density of the filler gradually decreased when the interval was extended by implanting a filler with the same density. The results confirmed that the size of the depletion layer between the filler and the N-epitaxy layer was reduced, and the current flowing along the N-epitaxy layer was increased. As the interval between the fillers decreased, the cost of the epitaxial process also decreased. However, it is possible to confirm the trade-off relationship that deteriorated the electrical characteristics and efficiency.
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Microstructure and Piezoelectric Properties of (Na,K)NbO3 System Ceramics Substituted with BNKZ
Jong-dae Han, Ju-hyun Yoo
J Korean Inst Electr Electron Mater Eng 2017;30(10):637-640.   Published online October 1, 2017
DOI: https://doi.org/10.4313/JKEM.2017.30.10.637
In this study, (1-x)(Na0.52K0.443Li0.037)(Nb0.883Sb0.08Ta0.037)O3-x(Bi0.5(Na0.7K0.3)0.5ZrO3 ceramics were fabricated by BNKZ substitution using a conventional solid-state method to develop excellent lead-free piezoelectric ceramics for piezoelectric actuators; their dielectric and piezoelectric properties were then investigated. All specimens were in the orthorhombic phase. NKL-NSTO3 ceramics with x=0.01 showed excellent piezoelectric properties. The density (ρ), piezoelectric charge constant (d33), planar piezoelectric coupling coefficient (kp), mechanical quality factor (Qm), and dielectric constant (εr) had optimized values of 4.56 g/㎤, 208 pC/N, 0.43, 96, and 975, respectively.
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A Study Comparison and Analysis of Electrical Characteristics of IGBTs with Variety Gate Structures
Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2016;29(11):681-684.   Published online November 1, 2016
DOI: https://doi.org/10.4313/JKEM.2016.29.11.681
This research was carried out experiments of variety IGBTs for industrial inverter and electric vehicle. The devices for this paper were planar gate IGBT, trench gate IGBT and dual gate IGBT and we designed using same design and process parameters. As a result of experiments, the electrical characteristics of planar gate IGBT were 1,459 V of breakdown voltage, 4.04 V of threshold voltage and 4.7 V of on-state voltage drop. And the electrical characteristics of trench gate IGBT were 1,473 V of breakdown voltage, 4.11 V of threshold voltage and 3.17 V of on-state voltage drop. Lastly, the electrical characteristics of dual gate IGBT were 1,467 V of breakdown voltage, 4.14 V of threshold voltage and 3.08V of on-state voltage drop. We almost knew that the trench gate IGBT was superior to dual gate IGBT in terms of breakdown voltage. On the other hand, the dual gate IGBT was better than the trench gate IGBT in terms of on state voltage drop.
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Study of the 1,200 V-Class Floating Island IGBT
Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2016;29(9):523-526.   Published online September 1, 2016
DOI: https://doi.org/10.4313/JKEM.2016.29.9.523
This paper was researched about 1,200 V level floating island IGBT (insulated gate bipolar transistor). Presently, 1,200 V level IGBT is used in Inverter for distributed power generation. We analyzed and compared electrical charateristics of the proposed floating island IGBT and conventional IGBT. For analyzing and comparison, we used T-CAD tool and simulated the electrical charateristics of the devices. And we extracted optimal design and process parameter of the devices. As a result of experiments, we obtained 1,456 V and 1,459 V of breakdown voltages, respectively. And we obatined 4.06 V and 4.09 V of threshold voltages, respectively. On the other hand, on-state voltage drop of floating island IGBT was 3.75 V. but on-state vlotage drop of the conventional IGBT was 4.65 V. Therefore, we almost knew that the proposed floating island IGBT was superior than the conventional IGBT in terms of power dissipation.
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Analysis of The Electrical Characteristics of Power IGBT According to Design and Process Parameter
Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2016;29(5):263-267.   Published online May 1, 2016
DOI: https://doi.org/10.4313/JKEM.2016.29.5.263
In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.
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The Fabrication of Super Junction IGBT with 3,000 V Class Super Junction Field Rings
Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2015;28(9):551-554.   Published online September 1, 2015
DOI: https://doi.org/10.4313/JKEM.2015.28.9.551
This paper was analyzed electrical characteristics of super junction IGBT with super junction field rings. As a result of super junction IGBT with super junction field rings, we obtained 3,300 V breakdown voltage and good thermal characteristics. we obtained shrinked chip size because field ring was decreased than field ring for conventional IGBT, too. And we fabricated super junction IGBT with super junction field rings. As a result of measuring fabricated chip, we obtained 3,300 V breakdown voltage. The fabricated devices were replaced thyristos using high voltage conversion, sufficiently.

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  • Characterization and Performance Evaluation of the Superjunction RB-IGBT in Matrix Converter
    Kun Zhou, Linhua Huang, Xiaorong Luo, Zhaoji Li, Juntao Li, Gang Dai, Bo Zhang
    IEEE Transactions on Power Electronics.2018; 33(4): 3289.     CrossRef
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The Develop of Super Junction IGBT for Using Super High Voltage
Hun Suk Chung, Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2015;28(8):496-500.   Published online August 1, 2015
DOI: https://doi.org/10.4313/JKEM.2015.28.8.496
This paper was proposed the theoretical research and optimal design 3000V super junction NPT IGBT for using electrical automotive and power conversion. Because super junction IGBT was showed ultra low on resistance, it was structure that can improve the thermal characteristics of conventional NPT IGBT. The electrical characteristics of super junction NPT IGBT were 2.52 V of on state voltage drop, 4.33 V of threshold voltage and 2,846 V breakdown voltage. We did not obtaing 3,000 V breakdown voltage but we will obtain 3,000 V breakdown voltage through improving p pillar layer. If we are carried this research, This device will be used electrical automotive, power conversiton and high speed train.
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The Optimal Design of Super High Voltage Planar Gate NPT IGBT
Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2015;28(8):490-495.   Published online August 1, 2015
DOI: https://doi.org/10.4313/JKEM.2015.28.8.490
This paper was proposed the theoretical research and optimal design 3,000 V IGBT for using electrical automotive, high speed train and first power conversion. To obtaining 3,000 V breakdown voltage, the design parameters was showed 160 Ω·cm resistivity and 430 ㎛ drift length. And to maintain 5 V threshold voltage, we obtained 6.5×1013 cm-2 p-base dose. We confirmed 24 ㎛ cell pitch for maintain optimal on state voltage drop and thermal characteristics. This 3,000 V IGBT was replaced to thyristor devices using first power conversion and high speed train, presently.
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Regular Paper : Effect of Surface Roughness on the Formation of Micro-Patterns by Soft Lithography
Kyung Ho Kim, Kyun Choi, Yoon Soo Han
J Korean Inst Electr Electron Mater Eng 2014;27(12):871-876.   Published online December 1, 2014
DOI: https://doi.org/10.4313/JKEM.2014.27.12.871
Efficiency of crystalline Si solar cell can be maximized as minimizing optical loss through antireflection texturing with inverted pyramids. Even if cost-competitive, soft lithography can be employed instead of photolithography for the purpose, some limitations still remain to apply the soft lithography directly to as-received solar grade wafer with a bunch of micro trenches on surface. Therefore, it is needed to develop a low-cost, effective planarization process and evaluate its output to be applicable to patterning process with PDMS stamp. In this study new surface planarization process is proposed and the change of micro scale trenches on the surface as a function of etching time is observed. Also, the effect of trenches on pattern quality by soft lithography is investigated using FEM structural analysis. In conclusion it is clear that the geometry and shape of trenches would be basic considerations for soft lithography application to low quality wafer.
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Regular Paper : Porosity Control in LSM Electrode Formation in Layered Plannar SOFC Module
Won Jun Lee, Dong Hun Yeo, Hyo Soon Shin, Dea Yong Jeong
J Korean Inst Electr Electron Mater Eng 2014;27(12):866-870.   Published online December 1, 2014
DOI: https://doi.org/10.4313/JKEM.2014.27.12.866
In solid oxide fuel cell system, yttria-stabilized zirconia is generally adopted as the electrolyte, which has high strength and superior oxygen ion conductivity, and the air electrode and the fuel electrode are attached to this. Recently, new structure of ``layered planar SOFC module`` was suggested to solve there liability problem due to the high temperature stability of a sealing agent and a binding material. In this study to materialize the air electrode in a layered planar SOFC module, the LSM ink was coated to form homogeneous electrode in the channel after the ink preparation. As the porosity control agent, PMMA oractive carbon powder was adopted with use of a commercial dispersant in ethanol. The optimal amounts of both the porosity control agents and the dispersant were determined. Four (4) vol% of the dispersant for the LSM-PMMA case and 15 vol% for LSM-carbon powder showed the lowest viscosities respectively to indicate the best dispersed states of the slurries. With PMMA and carbon powder, sintered LSM ink shows the relatively homogeneous distributions of pores and with increases of the agents, the porosities increased in both cases. From this, it can be thought that the amount of the PMMA or carbon powder could be used to control the porosity of the LSM ink.
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Light Source and Application Technology : Measurement of Optical Properties of a Liquid Based on a Side-polished Optical Fiber
Hyun Jin Lee, Kwang Taek Kim
J Korean Inst Electr Electron Mater Eng 2014;27(3):195-198.   Published online March 1, 2014
DOI: https://doi.org/10.4313/JKEM.2014.27.3.195
In this paper, a measurement method to obtain the optical properties of a liquid base on a side-polished single mode fiber was proposed and demonstrated. The device showed periodic resonance coupling against wavelengths. The refractive index and dispersion characteristics of a liquid were calculated by use of the spacings of periodic resonance wavelengths of the device. The thermo-optic coefficient of the liquid was obtained by monitering the shift of resonance wavelengths of the devices with change of environmental temperature.
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Study on the Design of DC-DC Converter for Super Junction MOSFET Battery Charger of Electric Vehicles
Bum June Kim, Yong Sung Hong, Gwan Pil Silm, Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2013;26(8):587-590.   Published online August 1, 2013
DOI: https://doi.org/10.4313/JKEM.2013.26.8.587
Release competition and development of eco-friendly vehicles have been conducted violently also automaker, it will be a high growth industry of the charger and battery, which is the driving source of the motor of an electric vehicle. Reduces the on-resistance power elements DC - DC converter for battery charger for electric vehicles, must minimize switching losses. Should have a low on-resistance power than existing products. Compare the Super Junction MOSFET and Planar MOSFET, As a result, super junction MOSFET improve on about 87.4% on-state voltage drop performance than planar MOSFET.
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Characterization and Comparison of Doping Concentration in Field Ring Area for Commercial Vertical MOSFET on 8” Si Wafer
Young Soo Kwon, Gwon Je Kim, Ye Hwan Kang
J Korean Inst Electr Electron Mater Eng 2013;26(4):271-274.   Published online April 1, 2013
DOI: https://doi.org/10.4313/JKEM.2013.26.4.271
Power Metal Oxide Semiconductor Field Effect Transistor`s (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an “ideal switch”. The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was 3 ㎛ and P base dose was 1e15 ㎠. Also the numerical multiple 2.52 ㎠ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from 1,150℃ to 1,200℃. And then 1,150℃ diffusion time was best condition for break down voltage.
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Study on Industrial Inverters for Driving High-efficiency High-voltage Field-stop IGBT Optimization Design
Myung Hwan Lee, Bum June Kim, Eun Sik Jung, Hun Suk Jung, Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2013;26(4):257-263.   Published online April 1, 2013
DOI: https://doi.org/10.4313/JKEM.2013.26.4.257
In this paper Solar, Wind, fuel cell used in a Power conversion devices and industrial inverter motor to increase the efficiency of energy consumption, which is a core part of high-efficiency, high-voltage Trench Gate Field Stop IGBT was studied. For this purpose Planar type NPT IGBT and Planar type Field Stop IGBT have designed a basic structure designed to Trench Gate Field Stop IGBT based on the completed structure by analyzing the energy consumption of electrical characteristics, efficiency is a key part, high-efficiency and high-voltage inverter for industry regarding the optimization design for Trench Gate Field Stop IGBT.
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Energy Materials : Coating of LSM Ink in the Layered Planar Type SOFC
Sung Il Lee, Dong Hun Yeo, Hyo Soon Shin, Young Soo Yoon
J Korean Inst Electr Electron Mater Eng 2012;25(7):552-557.   Published online July 1, 2012
DOI: https://doi.org/10.4313/JKEM.2012.25.7.552
In this study, we have coated the inner surface of YSZ channel using LSM powder ink through depressurization process for making the cathode of a stacked planar-type SOFC module. To coat the surface of YSZ channel uniformly, we tried to find the optimum manufacturing condition for LSM ink. We used four different dispersants (BYK series) and two different solvents (ethanol and DMF) to make the LSM ink. It was revealed that the ink made with the ethanol solvent and the BYK-111 dispersant has the lowest viscosity, relatively low contact angle and most excellent dispersibility. After depressurizing a chamber filled with LSM ink and sintered YSZ channel, we have found that the YSZ channel was uniformly coated with LSM cathode. The LSM ink with 25 vol% BYK-111 showed the most uniform coating.
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Energy Materials : The Warpage Phenomena of Electrolyte Layer During the Sintering Process in the Layered Planar SOFC Module
Min Wook Oh, Sin Il Gu, Hyo Soon Shin, Dong Hun Yeo
J Korean Inst Electr Electron Mater Eng 2012;25(3):241-246.   Published online March 1, 2012
DOI: https://doi.org/10.4313/JKEM.2012.25.3.241
A layered planer SOFC module was designed from planar-type SOFC. It was prepared by multi-layered ceramic technology. To form the cathode and the anode in the layered structure, reliable channels should be made on the both side of electrolyte perpendicularly. However, monolithic SOFC using multi-layered ceramic technology hasn`t been studied another group, and the warpage of electrolyte in the channel, also, hasn`t been studied, when electrode is printed on the electrolyte. In this study, the channels are prepared with electrode printing, and their warpage are evaluated. In the case of YSZ without electrode, the warpages are nothing in the limit of measurement using optical microscope. The warpage of ``YSZ-NiO printed`` increases than that of ``NiO printed``, and also, the case of ``double electrode printed`` is similar to ``YSZ-NiO printed``. It is thought that, in the printed electrolyte, the warpage is related to the difference of the sintering behavior of each material.
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A Study on High-voltage Low-power Power MOSFET of Optimization for Industrial Motor Drive
Bum June Kim, Hun Suk Chung, Seong Jong Kim, Eun Sik Jung, Ey Goo Kang
J Korean Inst Electr Electron Mater Eng 2012;25(3):170-175.   Published online March 1, 2012
DOI: https://doi.org/10.4313/JKEM.2012.25.3.170
Power MOSFET is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Recently attention to the motor and the application of various technologies. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters, motor controllers. In this paper, design the 600 V Planar type, and design the trench type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

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  • Reliability Test on Vienna Rectifier for Wide Bandgap Devices in EV Charging Systems
    Bharaneedharan Balasundaram, P. Suresh, Parvathy Rajendran, It Ee Lee, C. Ahamed Saleel
    IEEE Access.2025; 13: 3072.     CrossRef
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Effect of Pad Thickness on Removal Rate and Within Wafer Non-Uniformity in Oxide CMP
Jae Hyun Bae, Hyun Seop Lee, Jae Hong Park, Hideaki Nishizawa, Masaharu Kinoshita, Hae Do Jeong
J Korean Inst Electr Electron Mater Eng 2010;23(5):358-363.   Published online May 1, 2010
DOI: https://doi.org/10.4313/JKEM.2010.23.5.358

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  • Effects of CMP Retaining Ring Material on the Performance of Wafer Polishing
    Ki-Won Park, Eun-young Kim, Dong-Sam Park
    Journal of the Korean Society of Manufacturing Process Engineers.2020; 19(3): 22.     CrossRef
  • Effects of Insert Materials of Retaining Ring on Polishing Finish in Oxide CMP
    Ki-Won Park, Dong-Sam Park
    Journal of the Korean Society of Manufacturing Process Engineers.2019; 18(8): 44.     CrossRef
  • Finite Element Analysis on Dynamic Viscoelasticity of CMP Polishing Pad
    Byeongjun Pak, Dasol Lee, Seonho Jeong, Hyunjin Kim, Haedo Jeong
    Journal of the Korean Society for Precision Engineering.2019; 36(2): 177.     CrossRef
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RF High Power Amplifier Module using AIN Substrate
Seung Yong Kim, Choong Mo Nam
J Korean Inst Electr Electron Mater Eng 2009;22(10):826-831.   Published online October 1, 2009
DOI: https://doi.org/10.4313/JKEM.2009.22.10.826
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Characteristics of Catalytic Combustible Gas Sensor Based on Planar Technology
Yeong Bok Kim, Hyo Sub Noh, Jin Seong Park
J Korean Inst Electr Electron Mater Eng 2008;21(9):812-817.   Published online September 1, 2008
DOI: https://doi.org/10.4313/JKEM.2008.21.9.812
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The Design a Planar Patch Sensor Partial Discharge Diagnosis in 6.6 kV Rotating Machine Stator Windings
Kwang Jin Lim, Noh Joon Park, Hee Dong Kim, Young Ho Ju, Dae Hee Park
J Korean Inst Electr Electron Mater Eng 2008;21(5):481-485.   Published online May 1, 2008
DOI: https://doi.org/10.4313/JKEM.2008.21.5.481
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Polishing Pad Analysis and Improvement to Control Performance
J Korean Inst Electr Electron Mater Eng 2007;20(10):839-845.   Published online October 1, 2007
DOI: https://doi.org/10.4313/JKEM.2007.20.10.839
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A Study on 013㎛ Cu/Low-k Process Setup and Yield Improvement
J Korean Inst Electr Electron Mater Eng 2007;20(4):325-331.   Published online April 1, 2007
DOI: https://doi.org/10.4313/JKEM.2007.20.4.325
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Planarizaiton of Cu Interconnect using ECMP Process
J Korean Inst Electr Electron Mater Eng 2007;20(3):213-217.   Published online March 1, 2007
DOI: https://doi.org/10.4313/JKEM.2007.20.3.213
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A Studying on the Crosstalk Characteristic of mm-wave Coplanar-waveguide
J Korean Inst Electr Electron Mater Eng 2006;19(2):158-161.   Published online February 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.2.158
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Optimization of Capacitor Threshold V(T) Implantation for Planar P-MOS DRAM Cell
J Korean Inst Electr Electron Mater Eng 2006;19(2):126-129.   Published online February 1, 2006
DOI: https://doi.org/10.4313/JKEM.2006.19.2.126
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