Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

In parallel with the efforts to improve the device performance in modern integrated circuits, it is necessary to downscale their core components, field-effect transistors (FETs), generally gauged by their physical gate length. Upon such device scaling, the emergence of the short-channel effect impedes further scaling into the nanometer scale in the silicon VLSI (Very-Large-Scale-Integration) system. To address this issue, two-dimensional (2D) semiconductors, leveraging their atomically thin thickness and dangling-bond-free characteristics, are being highlighted as a material solution for future scaling technology without severe mobility degradation. Despite the expected ideal physical properties, 2D semiconductors have yet to realize their full potential owing to the limited development of integration technology. In this context, we survey and review the tailored van der Waals integration technologies for 2D FETs. In particular, we provide an in-depth study of both van der Waals integrated contact and dielectric methods along with an explanation of customized materials. In essence, this van der Waals integrationcentered approach will be a core strategy to implement the high-performance 2D transistors that meet the demand of FET miniaturization.

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

Ion-beam sputtering (IBS) was used to deposit semiconducting IZTO (indium zinc tin oxide) thin films onto heavily-doped Si substrates using a sintered ceramic target with the nominal composition In_0.4Zn_0.5Sn_0.1O_1.5, which could work as a channel layer for oxide TFT (oxide thin film transistor) devices. The crystallization behavior and electrical properties were examined for the films in terms of deposition parameters, i.e. target tilt angle and substrate temperature during deposition. The thickness uniformity of the films were examined using a stylus profilometer. The observed difference in electrical properties was not related to the degree of crystallization but to the deposition temperature which affected charge carrier concentration (n), electrical resistivity (ρ), sheet resistance (R_s), and Hall mobility (μH) values of the films.

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

Atomically thin MoS₂ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, MoS₂ single-crystal as a transistor channel after transfer onto a SiO2/Si substrate. The MoS2 FETs displayed n-channel characteristics with an electron mobility of 0.05 cm²/V-sec, and a current on/off ratio of ION/IOFF?5×10⁴. Application of bottom-gate voltage stresses, however, increased the interface charges on MoS2/SiO₂, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

Resistive random access memory (ReRAM) of metallic conduction channel mechanism is based on the electrochemical control of metal in solid electrolyte thin film. Amorphous chalcogenide materials have the solid electrolyte characteristic and optical reactivity at the same time. The optical reactivity has been used to improve the memory switching characteristics of the amorphous As2Se3-based ReRAM. This study focuses on the formation of holographic lattices patterns in the amorphous As2Se3 thin film for straight conductive channel. The optical parameters of amorphous As2Se3 thin film which is a refractive index and extinction coefficient was taken by n&k thin film analyzer. He-Cd laser (wavelength: 325 nm) was selected based on these basic optical parameters. The straighten conduction channel was formed by holographic lithography method using He-Cd laser. Ag+ ions that photo-diffused periodically by holographic lithography method will be the role of straight channel patterns. The fabricated ReRAM operated more less voltage and indicated better reliability.

This paper presents a ZigBee wireless communication system for remote diagnosis in overhead distribution power lines. The system is divided in three parts in the functional aspect - a host computer module, a remote controller module and a diagnostic system module. The host computer module designed as USB interface transmits control signals and receive data measured by sensor. The remote controller module operates the diagnostic system. Diagnostic system module communicates with internal main controller and host computer USB. Multiple communication channel is adopted for simultaneous operations of several diagnostic system. Dedicated protocol for each module is developed. The system is designed with a focus on low cost and small size suitable for lightweight and small diagnostic system.

In this paper, TiO2 based thin-film transistors (TFTs) were fabricated using by an atomic layer deposition with high aspect ratio and excellent step coverage. Ti02 semiconducting layer was deposited showing a rutile phase through the rapid thermal annealing process, and exhibited TFT characteristics with a 200 pm channel length of low-leakage currents (none of current flow during off-state), stable threshold voltages (-10 V - 0 V), and a much higher on/off current ratio (