Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Articles

50 nm 급 낸드플래시 메모리에서의 Program/Erase 스피드 측적을 통한 트랩 생성 분석

김병택, 김용석, 허성희, 유장민, 노용한

Trap Generation Analysis by Program/Erase Speed Measurements in 50nm Nand Flash Memory

Byoung Taek Kim, Yong Seok Kim, Sung Hoi Hur, Jang Min Yoo, Yong Han Roh
J Electr Electron Mater 2008;21(4):300-304.
Published online: April 1, 2008
  • 10 Views
  • 0 Download
  • 0 Crossref
  • 0 Scopus
prev next

Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:

Include:

Trap Generation Analysis by Program/Erase Speed Measurements in 50nm Nand Flash Memory
J Electr Electron Mater. 2008;21(4):300-304.   Published online April 1, 2008
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Trap Generation Analysis by Program/Erase Speed Measurements in 50nm Nand Flash Memory
J Electr Electron Mater. 2008;21(4):300-304.   Published online April 1, 2008
Close