Field-effect transistors (FETs) are the key elements of conventional electronics; hence, have drawn a lot of research and commercial interests. In recent years, metal halide perovskite materials have achieved a remarkable efficiency of 29.15% in the field of photovoltaics, and have drawn the scientific community’s attention to promote their use in the field of optoelectronics, such as FETs and phototransistors. The MAPbI3 (methylammonium lead iodide) perovskite TFT has achieved a record hole mobility of 21.41 ㎠/V-s in the year 2020. In this review, we will briefly discuss the physical structure of MAPbI3 perovskite and the essential factors that stimulate these devices, together with the role of defects, the ion migration concept, and the implication of both dielectric and electrode materials on the device’s performance.
Ion-beam sputtering (IBS) was used to deposit semiconducting IZTO (indium zinc tin oxide) thin films onto heavily-doped Si substrates using a sintered ceramic target with the nominal composition In0.4Zn0.5Sn0.1O1.5, which could work as a channel layer for oxide TFT (oxide thin film transistor) devices. The crystallization behavior and electrical properties were examined for the films in terms of deposition parameters, i.e. target tilt angle and substrate temperature during deposition. The thickness uniformity of the films were examined using a stylus profilometer. The observed difference in electrical properties was not related to the degree of crystallization but to the deposition temperature which affected charge carrier concentration (n), electrical resistivity (ρ), sheet resistance (Rs), and Hall mobility (μH) values of the films.
High reliability thin film transistors are important factors for next-generation displays. The reliability of transparent a-IGZO semiconductors is being actively studied for display applications. A plasma treatment can fill the oxygen vacancies in the channel layer and the channel layer/insulating layer interface so that the device can work stably under a bias voltage. This paper studies the effect of plasma treatment on the performance of a-IGZO TFT devices. The influence of different plasma gases on the electrical parameters of device and its working reliability are reviewed. The article mentions argon, fluorine, hydrogen and several ways of processing in the atmosphere. Among these methods, F (fluorine) plasma treatment can maximize equipment reliability. It is expected that the presented results will form a basis for further research to improve the reliability of a-IGZO TFT.
The formation of inorganic thin films in low-temperature solution processes is necessary for a wide range of commercial applications of organic electronic devices. Aluminum oxide thin films can be utilized as barrier films that prevent the deterioration of an electronic device due to moisture and oxygen in the air. In addition, they can be used as the gate insulating layers of a thin film transistor. In this study, aluminum oxide thin film were formed using two methods simultaneously, a thermal process and the DUV process, and the properties of the thin films were compared. The result of converting aluminum nitrate hydrate to aluminum oxide through a hybrid process using a thermal treatment and DUV was confirmed by XPS measurements. A film-based a-IGZO TFT was fabricated using the formed inorganic thin film as a gate insulating film to confirm its properties.
Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.
Thin film transistors (TFTs) with large-area, high mobility, and high reliability are important factors for next-generation displays. In particular, thin transistors based on IGZO oxide semiconductors are being actively researched for this application. In this study, several methods for improving the reliability of a-IGZO TFTs by applying various materials on a passivation layer are investigated. In the literature, inorganic SiO2, TiO2, Al2O3, ZTSO, and organic CYTOP have been used for passivation. In the case of Al2O3, excellent stability is exhibited compared to the non-passivation TFT under the conditions of negative bias illumination stress (NBIS) for 3 wavelengths (R, G, B). When CYTOP passivation, SiO2 passivation, and non-passivation devices were compared under the same positive bias temperature stress (PBTS), the Vth shifts were 2.8 V, 3.3 V, and 4.5 V, respectively. The Vth shifts of TiO2 passivation and non-passivation devices under the same NBTS were -2.2 V and -3.8 V, respectively. It is expected that the presented results will form the basis for further research to improve the reliability of a-IGZO TFT.
The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.
In this study, a femtosecond laser pre-annealing technology based on indium zinc oxide (IZO) thin-film transistors (TFTs) was investigated. We demonstrated a stable pre-annealing process to analyze the change in the surface structures of thin-films, and we improved the electrical performance. Furthermore, static and dynamic electrical characteristics of IZO TFTs with n-channel inverters were observed. To investigate the static and dynamic responses of our solution-processed IZO TFTs, simple resistor-load-type inverters were fabricated by connecting a 1-MΩ resistor. The femtosecond laser pre-annealing process based on IZO TFTs showed good performance: a field-effect mobility of 3.75 cm2/Vs, an Ion/Ioff ratio of 1.8×105, a threshold voltage of 1.13 V, and a subthreshold swing of 1.21 V/dec. Our IZO-TFT-based N-MOS inverter performed well at operating voltage, and therefore, is a good candidate for advanced logic circuits and display backplane.
We investigated solution-processed indium-zinc oxide (IZO) thin-film transistors (TFTs) by inserting a 2-(4- biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) buffer layer. This buffer layer efficiently tuned the energy level between the semiconducting oxide channel and metal electrode by increasing charge extraction, thereby enhancing the overall device performance: the IZO TFT with embedded PBD layer (thickness: 5 nm; width: 2,000 μm; length: 200 μm) exhibited a field-effect mobility of 1.31 cm2V-1s-1, threshold voltage of 0.12 V, subthreshold swing of 0.87 V decade-1, and on/off current ratio of 9.28×105.
We investigated solution-processed indium-yttrium-oxide (IYO) TFTs using apoly (methyl methacrylate) (PMMA) passivation layer. The IYO semiconductor solution was prepared with 0.1 M indium nitrate hydrate and 0.1 M yttrium acetate dehydrate as precursor solutions. The solution-processed IYO TFTs showed good performance: field-effect mobility of 13.13 ㎠/Vs, a threshold voltage of 8.2 V, a subthreshold slope of 0.93 V/dec, and a current on-to-off ratio of 7.2 × 106. Moreover, the PMMA passivation layers used to protectthe IYO active layer of the TFTs, did so without deteriorating their performance under ambient conditions; their operational stability and electrical properties also improved by decreasing leakage current.
We report on amorphous thin-film transistors (TFTs) with indium zinc oxide (IZO) channel layers that were fabricated via a solution process. We prepared the IZO semiconductor solution with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions. The solution- processed IZO TFTs showed good performance: a field-effect mobility of 7.29 ㎠/Vs, a threshold voltage of 4.66 V, a subthreshold slope of 0.48 V/dec, and a current on-to-off ratio of 1.62×105. To investigate the static response of our solution-processed IZO TFTs, simple resistor load-type inverters were fabricated by connecting a 2-MΩ resistor. Our IZOTFTbased N-MOS inverter performed well at operating voltage, and therefore, isa good candidate for advanced logic circuits and display backplane.
In this study, p-type thin film transistors consisting of CuO channels were fabricated by sol-gel process, with copper (II) acetate monohydrate precursors. At 500℃, the deposited films were fully converted into monoclinic phase CuO. The fabricated CuO thin film transistors deliver field effect mobility in saturation regime of 0.015㎠/Vs, and Ion/Ioff of ~10³. The degradation of the performance of the fabricated CuO thin film transistor caused by the exposure to air has been studied.
In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.
In this study, we fabricate transparent and bendable a-IGZO (amorphous indium gallium zinc oxide) TFTs (thin-film transistors) with a-IZO (amorphous indium zinc oxide) transparent electrodes on plastic substrates and investigate their electrical characteristics under bending states. Our a-IGZO TFTs show a high transmittance of 82% at a wavelength of 550 nm. And these TFTs have an Ion/Ioff ratio of 1.8×108, a field effect mobility of 15.4 cm2/V·s, and a subthreshold swing of 186 mV/dec. The good electrical characteristics are retained even after bending with a curvature radius of 18 mm corresponding to a strain of 0.5% owing to mechanical durability of the transparent electrodes used in this study.
The ultimate aims of display market is transparent or flexible. Researches have been carried out for various applications. It has been possible to reduced the process steps and get good electrical properties for semiconductors with large optical bandgaps. Oxide semiconductors have been established as one of the leading and promising technology for next generation display panels. In this paper, alternative treatment processes have been tried for oxide semiconductors of thin film transistors to increase the electrical properties of the thin film transistors and to investigate the mechanisms. There exist a various oxide semiconductors. Here, we focused on InGaZnO, ZnO and InSnZnO which are commercialized or researched actively.
Recently, ZnO based oxide TFTs used in the flexible and transparent display devices are widely studied. To apply to OLED display switching devices, electrical performance and stability are important issues. In this study, to improve these electrical properties, we fabricated TFTs having Al doped Zinc Oxide (AZO) layer inserted between the gate insulator and ZnO layer. The AZO and ZnO layers are deposited by Atomic layer deposition (ALD) method. I-V transfer characteristics and stability of the suggested devices are investigated under the positive gate bias condition while the channel defects are also analyzed by the photoluminescence spectrum. The TFTs with AZO layer show lower threshold voltage (Vth) and superior sub-threshold slop. In the case of Vth shift after positive gate bias stress, the stability is also better than that of ZnO channel TFTs. This improvement is thought to be caused by the reduced defect density in AZO/ZnO stack devices, which can be confirmed by the photoluminescence spectrum analysis results where the defect related deep level emission of AZO is lower than that of ZnO layer.
We have investigated the effect of electrical properties of amorphous InGaZnO thin filmtransistors (a-IGZO TFTs) by post thermal annealing in O2 ambient.The post-annealed in O2 ambienta-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has betterperformance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well asreasonable threshold voltage, than others do. The interface trap density is controlled to achieve theoptimum value of TFT transfer and output characteristics. The device performance is significantlyaffected by adjusting the annealing condition. This effect is closely related with the modulation annealingmethod by reducing the localized trapping carriers and defect centers at the interface or in the channellayer.
We investigated the characteristics of the silicon oxy-nitride and nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) at the low temperature with a varying NH3/N2O mixing ratio and a fixed SiH4 flow rate. The deposition temperature was held at 150℃ which was the temperature compatible with the plastic substrate. The composition and bonding structure of the nitride films were investigated using Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). Nitrogen richness was confirmed with increasing optical band gap and increasing dielectric constant with the higher NH3 fraction. The leakage current density of the nitride films with a high NH3 fraction decreased from 8X10-9 to 9X10-11(A/cm2 at 1.5 MV/cm). This results showed that the films had improved electrical properties and could be acceptable as a gate insulator for thin film transistors by deposited with variable NH3/N2O mixing ratio.
In this paper, we analyzed the effects of the number of TIPS-pentacene droplets and also the substrate temperature on the performance of OTFTs As the number of the droplets increased, the mobility increased and reached the perk value and then reduced at all temperatures. The peak mobility was 0.14 ± 0.03 cm²/V sec at 3 droplets and 41℃, 0.19 ± 0.02 cm²/V.sec at 4 droplets and 46℃,and 0.35 ± 0.10 cm²/V sec at 7 droplets and 51℃. The reason of existence of peak mobility can be found in matching the evaporation of solvent with the velocity of crystal formation. When two parameters were properly matched, the mobility produced the highest.
In this paper the author proposes a method of implementing a numerical model for threshold voltage (V_th) shift in organic thin-film transistors (QTFTs) into SPICE tools. V_th shift is first numerically modeled by dividing the shift into sequentially ordered groups. The model is then used to derive a simulations model which takes into simulation parameters and calculation complexity. Finally, the numerical and simulation models are implemented in AIM-SPICE. The SPICE simulation results agree well with the V_th shift obtained from an OTFT fabricated without any optimization. The proposed method is also used to implement the stretched-exponential time dependent V_th shift in AIM-SPICE and the results show the proposed method is applicable to various types of V_th shifts.
In this study, the influence of the intermolecular distance on the charge mobility in a pentacene thin-film was investigated. In order to increase the mobility which depends on the π-overlap between molecules, the intermolecular distance was shortened by compressive force along the conduction channel. Pentacene thin-film was fabricated on flexible substrates bent outward at different radii to stretch the gate dielectric surface and then the substrates were unbent, producing the compressive force to the film. The result showed that the mobility increased proportionally to the strain applied during the pentacen deposition and the molecular packing inside a grain was not optimal for the charge transport.
In this paper, the properties of SnZnO films obtained from solution process with different component fractions were compared. The thermal behavior of the SnZnO solutions showed only a slight change according to the component fraction change. However, the definite changes were revealed at the structural properties of the SnZnO films. With diverse analyses, the origin of the changes was proved to the influence of phase change from SnO2 to ZnO in SnZnO lattice. With the SnO2-phase-dominant SnZnO, the highest field effect mobility and on/off ratio of about 8.6 cm2/Vs and 2 × 108 were achieved, respectively.
In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density (Dit) and grain boundary trap density (Ntrap) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.
In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT`s. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT`s due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.
Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 cm2/Vs, the threshold voltage (Vth) of 2.1 V, the on/off ratio of 4.95×10(6), and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are temporarily trapped in the gate insulator, the semiconductor, or the interface between both layers.
In this paper a printing process for patterning electrodes on large area substrate was developed by combining screen printing with reverse off-set printing. Ag ink was uniformly coated by screen printing. And then etching resist (ER) was patterned in the Ag film by reverse off-set printing, and then the non-desired Ag film was etched off by etchant. Finally, the ER was stripped-off to obtain the final Ag patterns. We extracted the suitable conditions of reverse Using the process we successfully fabricated gate electrodes and scan bus lines of OTFT-backplane used for e-paper, in which the diagonal size was 6 inch, the resolution 320x240, the minimum line width 30 um, and sheet resistance 1 Ω/□.
In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to 90℃ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; O2 Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as 0.63 cm2 V-1s-1, 1.7 x 10(-6), and of 0.75 V/decade, respectively.
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