An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

A variable vacuum capacitor (VVC), which is a variable element, is used to match impedance in plasma that changes with various impedance values, and its use is expanding with the rapid growth of the semiconductor business. Since VVCs have to secure insulation performance and vary capacitance within a compact size, electrode design and manufacturing are very important; thus, various technologies such as part design and manufacturing technology and vacuum brazing technology are required. In this study, based on the model of an advanced foreign company that is widely used for impedance matching in the manufacture of semiconductors and displays, a VVC that can realize the same performance was developed. The electrode part was designed, the consistency was confirmed through analysis, and the precision of capacitance was improved by designing a cup-type electrode to secure the concentricity of the electrode. As a result of the evaluation, all requirements was satisfied. We believe that self-development will be possible if satisfactory responses are received through evaluation by VVC consumers in the future.

A pressure sensor is a device that converts an applied physical pressure into an electrical signal. Such sensors have a range of applications depending on the pressure level, from low to high pressure. Sensors that use physical pressure, when compared to those operating under air pressure, are not widely applied as they are inefficient. To solve this problem, graphene oxide, which exhibits good mechanical and electrical characteristics, was used to increase the efficiency of these pressure sensors. Graphene oxide has properties that control the movement of charges within the dielectric. Exploiting these properties, we evaluated the change in electrical characteristics when pressure was applied according to the ratio and thickness of the oxidation graph added to the pressure sensor.

Electric double layer capacitors (EDLCs) are promising candidates for energy storage devices in electronic applications. An EDLC yields high power density but has low specific capacitance. Carbon material is used in EDLCs owing to its large specific surface area, large pore volume, and good mechanical stability. Consequently, the use of carbon materials for EDLC electrodes has attracted considerable research interest. In this paper, in order to evaluate the electrochemical performance, graphene is used as an EDLC electrode with flake sizes of 3, 12, and 60 nm. The surface characteristic and electrochemical properties of graphene were investigated using SEM, BET, and cyclic voltammetry. The specific capacitance of the graphene based EDLC was measured in a 1 M TEABF₄/ACN electrolyte at the scan rates of 2, 10, and 50 mV/s. The 3 nm graphene electrode had the highest specific capacitance (68.9 F/g) compared to other samples. This result was attributed to graphene’s large surface area and meso-pore volume. Therefore, large surface area and meso-pore volume effectively enhances the specific capacitance of EDLCs.

In this study, the thermal degradation properties of polyethylene terephthalate film has been examined by the capacitance, Tan δ, thermography, FTIR, and SEM results at temperatures of 90~170℃ and frequencies of 0.3~3,000 kHz. It was found that the capacitance decreased with increasing thermal imaging temperature, probably caused by weakening of chemical bond with increasing temperature. Tan δ decreased upon increasing temperature from 90℃ to 170℃, probably due to the molecular motion of COOH radical or OH radical. The FT-IR measurement reveals that no structural change of the material occurs upon thermal radiation. The SEM measurement shows that the material is stabilized by thermal decomposition with increasing temperature; however, excessive thermal degradation obstructs the stabilization of the material.

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

The Sr0.7Bi2.3Nb2O9(SBN) thin films are deposited on Pt electrode(Pt/Ti/SiO2/Si) using RF sputtering method at various deposition temperature. The deposition temperature of optimum was 300℃. SBN thin films were annealed at 500∼700℃ using furnace and RTA, respectively. The surface roughness showed about 2.42 nm in annealing temperature(600℃) of furnace. The capacitance density of SBN thin films were increased with the increase of annealing temperature. The maximum capacitance density of 0.7 ㎌/㎠was obtained by annealing temperature(700℃). The frequency dependence of dielectric loss showed about 0.03 in frequency ranges of 1∼1,000 kHz.

In this paper, we fabricated ceramic body and sapphire wafer in order to develop a hydraulic pressure sensor with high sensitivity and high temperature stability. The sapphire wafer was adopted with a membrane of capacitance ceramic pressure sensor. The capacitance value of the sensor for the finite element analysis(FEM) showed a linear pressure characteristics. Membrane was processed with a diameter of 32.4 ㎜ and a thickness of 1 ㎜ by using alumina powders. Ceramic body was processed with a diameter 32.4 ㎜ and a thickness 5 ㎜. The capacitance pressure sensor was made with high heat treatment of the ceramic body and the sapphire wafer. Initially capacitance of the pressure sensor was 50 pF and a capacitance of 110 pF was measured from 5 bar pressure. Output voltage of 5 V was appeared at 5 bar pressure.

The Sr based ceramic thin films were deposited on Si substrate by RF magnetron sputtering method. And Sr based thin films were annealed at 500～700℃ using RTA. The surface roughness showed about 2.4 nm in annealed thin film at 600℃. The capacitance density of Sr based thin films were increased with the increase of annealing temperature. The maximum capacitance density of 0.6 ㎌/㎠ was obtained by annealing temperature at 700℃. The voltage dependence of dielectric loss showed about 0.02 in voltage ranges of -10～＋10 V. The leakage current density of annealing temperature of 600℃ was the 4.0×10-6 A/㎠ at applied voltage of -5～＋5 V.

The K-PCS and W-CDMA dual band dielectric duplexer and bandpass filters have been designed and fabricated. The dual band duplexer consists of the separate monoblock K-PCS and W-CDMA duplexers using common antenna port. The coupling capacitance and I/O impedance matching have been designed to minimize the cross interference between the bands. Isolations of crosspoint between Tx and Rx in K-PCS and W-CDMA dualband were about 47 dB and 100 dB, respectively. On the other hand, isolations of Tx and Rx in K-PCS and W-CDMA were about 66 dB and 65 dB, respectively. The difference between 47 dB and 100 dB originated from the different center frequencies in Tx and Rx of K-PCS and W-CDMA bands. The coupling capacitance of the bandwidth, I/O capacitance of I/O matching and impedance matching, and various capacitances were important role to fabricate the dielectric duplexer and bandpass filters.

This research, integratable capacitive relative humidity sensor was produced using polyimide on glass substrate. Also, at the time of upper electrode formation, upper electrode grain size was affected by giving changes to sputtering condition. Through this analyzing electrical characteristics affect from capacitive relative humidity sensor was possible. Capacitance of capacitive relative humidity sensor was 330 pF, linearity of 0.6%FS and it showed less than 3% of low hysterisis. Specially, hysterisis was affected more from interface than interstitial. Also was affected by the grain size which is one of the formation condition of upper electrode.