Silicon carbide (SiC) MOSFETs provide superior performance compared to traditional silicon devices under hightemperature and high-power conditions, making them particularly valuable for power electronics applications requiring highfrequency switching and high-energy efficiency. As the electric vehicle (EV) market expands, these devices are commonly packaged into six-pack modules, which can show their different electrical characteristics between the bare-die device and the package due to packaging that improves heat dissipation and other properties. This study uses bare-die SiC MOSFETs to explore their intrinsic characteristics and evaluate their performance in a half-bridge configuration. A half-bridge circuit was constructed, and performance was assessed by varying driving frequencies (10 kHz and 50 kHz) and adjusting the duty cycle between 20% and 80%. Analysis revealed that, at a fixed switching frequency, the average output voltage and average output current are proportional to the duty cycle.

Ga₂O₃ is an ultra-wide bandgap semiconductor material that offers superior electrical properties for high-voltage power electronics but suffers from poor thermal conductivity compared to conventional semiconductors. To overcome this thermal limitation, we developed Ga₂O₃/4H-SiC heterojunction Schottky barrier diodes that utilize the high thermal conductivity of SiC substrates. Using the aerosol deposition method, we successfully fabricated devices with different Ga₂O₃ film thicknesses (0.8-1.4 μm) and achieved exceptional electrical performance with the 0.8 μm device showing a specific on-resistance of 41 mΩ·cm² and a leakage current as low as 1.26 × 10^-10 A/cm² while maintaining stable operation up to 200℃. The devices demonstrated breakdown voltages reaching 2,365 V and maintained excellent rectification ratios above 1010 even at elevated temperatures. All fabricated devices with different film thicknesses showed consistent high-temperature stability, confirming the effectiveness of the heterojunction approach. These results provide a viable pathway for developing thermally stable, high-performance power devices essential for next-generation electric vehicle and renewable energy applications

The 4H-SiC VDMOSFET demonstrates a high reverse breakdown voltage (BV) due to the JFET region but experiences relatively high on-resistance (R_on). A widely adopted method to reduce the R_on is to uniformly increase the doping concentration of the JFET region, which results in a trade-off that reduces the BV. This study proposes a method to optimize the segmentation of the JFET region by selectively increasing the doping concentration using ‘total doping’, ‘half-doping’, and ‘quarter-doping’. The optimized quarter segment with a specific doping concentration slightly reduces BV, but the sharp decrease in specific on-resistance (R_on,sp) results in a 105% improvement in the performance index, Baliga’s Figure of Merit (BFOM). This research suggests the potential for electrically superior designs by modifying the doping concentration in the JFET region of conventional VDMOSFET structures.

4H-Silicon carbide (4H-SiC) is a promising material for power and harsh environment devices owing to its superior material properties, including wide bandgap, high critical electric field, and high thermal conductivity. However, despite the advantages of 4H-SiC, its channel mobility is reduced due to the high interface defect density between SiC and the oxide film, leading to increased device switching loss. Therefore, it is necessary to develop new fabrication methods to improve the quality of the SiO₂/4H-SiC interface. According to recent research, the effect of high-temperature (1,250~1,300℃) nitric oxide (NO) annealing on the interface states of SiO₂/4H-SiC and the channel mobility of 4H-SiC metal-oxide-semiconductor-field-effect transistors (MOSFETs) were investigated. Previous studies have optimized the NO post-oxidation annealing (POA) process, using N₂ diluted NO at 1,300℃ to reduce the high SiO₂/4H-SiC interface trap density (D_it). This paper focuses on high-temperature (1,250℃) 10% NO annealing to reduce interface defects by integrating nitrogen atoms into the oxide layer near the SiC interface, potentially increasing the channel mobility. Electrical properties such as D_it, threshold voltage (V_th), field-effect mobility (μ_FE), and specific on-resistance (R_on,sp) were assessed through capacitance-voltage (C-V) and current-voltage (I-V) measurements. It has been confirmed that the interface defect density of the gate oxide film was effectively improved under the POA conditions of 10% NO for 1 hour at 1,250℃.

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the Dit.

Nickel oxide is a nonstoichiometric transparent conductive oxide with p-type conductivity, a wide-band energy gap of 3.4~4.0 eV, and excellent chemical stability, making it a very important candidate as a material for bipolar devices.P-type conductivity in Transparent Conductive Oxides (TCO) is controlled by the oxygen vacancy concentration. During the TCO film deposition process, additional oxygen diffusing into the NiO structure causes the formation of Ni 3p ions and Ni vacancies. This eventually affects the hole concentration of the p-type oxide thin film. In this work, the surface morphology and the electrical characteristics were confirmed in accordance with the annealing atmosphere of the nickel oxide thin film.

Despite otherwise advantageous properties, the performance and reliability of devices manufactured in ß-Ga₂O₃ on semi-insulating Ga₂O₃ substrates may degrade because of poorly mitigated self-heating, which results from the low thermal conductivity of Ga₂O₃ substrates. In this work, we investigate and compare self-heating and device performance of β-Ga₂O₃ MESFETs on substrates of semi-insulating Ga₂O₃ and 4H-SiC. Electron mobility in β-Ga₂O₃ is negatively affected by increasing lattice temperature, which consequently also negatively influences device conductance. The superior thermal conductivity of 4H-SiC substrates resulted in reduced ß-Ga₂O₃ lattice temperatures and, thus, mitigates MESFET drain current degradation. This, in turn, allows practically reduced device dimensions without deteriorating the performance and improved device reliability.

We investigated deep levels in n-type 4H-SiC epitaxy layer of the Schottky barrier diodes (SBD) and Junction Barrier Schottky (JBS) diodes by using deep level transient spectroscopy (DLTS). The I-V characteristics of the JBS devices show ~100 times lower leakage current level than SBDs owing to the grid structures in JBS. The reliable responses of the diodes for deep level transient analysis showed from C-V characteristics. Several deep electron traps were revealed by DLTS measurements in epitaxial layers in 4H-SiC. In both types of diodes, the peaks corresponding to shallow energy levels were observed with slightly different values of 0.132 eV for JBS and 0.186 eV for SBDs. The two remarkable deep level peaks (J2 and J3) have been obtained with 0.257 eV and 0.273 eV in JBS, and they were analyzed to have a similar trap concentration of ~10¹⁴ cm^-3. The comparison results showed that the defects could be related with device fabrication procedures such as ion-implantation and growth.

In this work, we have investigated the effect of a 30-min thermal anneal at 550℃ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from 1×10¹⁵ cm^-3 to 5×10¹⁶ cm^-3 and the thickness from 0 μm to 9 μm. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

The temperature dependent characteristics on the properties of SiC Schottky Diode has beeninvestigated. In this study, the temperature dependent current-voltage characteristics of the SiC Schottkydiode were measured in the range of 300 ∼ 500 K. Divided into pre- and post- irradiated device wasmeasured. The barrier height after irradiation device at 500 K increased 0.15 eV compared to 300 K, thebarrier height of pre- neutron irradiated Schottky diode increased 0.07 eV. The effective barrier heightafter irradiation increased from 0.89 eV to 1.05 eV. And ideality factor of neutron irradiated Schottkydiode at 500 K decreased 0.428 compared to 300 K, the ideality factor of pre- neutron irradiated Schottkydiode decreased 0.354. Also, a slight positive shift in threshold voltage from 0.53 to 0.68 V. we analyzedthe effective barrier height and ideality factor of SiC Schottky diode as function of temperature.

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/SiO2structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatb and voltage (VFB) shift was positive. Near-interface trap charge density (Nit) and negative oxide trap charge density (Nox) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitorsis higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

Al2O3 films on silicon carbide were fabricated by Aerosol deposition with annealing temperatureat 800℃ and 1,000℃. The effect of thermal treatment on physical properties of Al2O3 thin films has beeninvestigated by XRD (X-ray diffraction), AFM (atomic force microscope), SEM (scanning electronmicroscope), and AES (auger electron spectroscopy). Also electrical properties have been investigated byKeithley 4,200 semiconductor parameter analyzer to explain the interface trapped charge density (Dit),flatband voltage (VFB) and leakage current (Io). Al2O3 films become crystallized with increasingtemperature by calculating full width at half maximum (FWHM) of diffraction peaks, also surfacemorphology is observed by topography measurement in non-contact mode AFM. Dit was 2.26×10-12eV-1.cm-2 at 800℃ annealed sample, which is the lowest value in all samples. Also the sample annealedat 800℃ has the lowest leakage current of 4.89×10-13 A.

The effect of neutron irradiation on the properties of SiC Schottky Diode has been investigated. SiC Schottky diodes were irradiated under neutron fluences and compared to the reference samples to study the radiation-induced changes in device properties. The condition of neutron irradiation was 3.1×1010n/cm2. The current density after irradiation decreased from 12.7 to 0.75 A/cm2. Also, a slight positive shift (ΔVth= 0.15 V) in threshold voltage from 0.53 to 0.68 V and a positive change (ΔΦB= 0.16 eV) of barrier height from 0.89 to 1.05 eV have been observed by the neutron irradiation, which is attributed to charge damage in the interface between the metal and the SiC layer.

Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (∼2.3 MV/cm), and high bulk electron mobility (∼900 cm2/Vs). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage (VB= 1,600 V), lower on-resistance (Ron= 0.43 mΩ·cm2) than Si-IGBT. Also,we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

ZnO nanowires on the a-, c- and m-plane oriented 4H-SiC substrates were grown by using a high temperature tube furnace, Ti/Au electrodes were deposited on ZnO nanowires and a-, c- and m-plane 4H-SiC substrates, respectively. The shape and density of the ZnO nanowires were inestigated by field emission scanning electron microscope. It was found that the growth direction of nanowires depends strongly on growth parameters such as growth temperature and pressure. In this work, The sensitivity of nanowires formed a-, c- and m-plane oriented 4H-SiC gas sensor was measured at 300℃ with CO gas concentration of 80%. The nanowires grown on a-plane oriented 4H-SiC show improved performance than those on c- and m-plane oriented 4H-SiC due to the increased density of nanowire on a plane 4H-SiC.

ZnO thin films were deposited on a-, c- and m- plane oriented 4H-SiC substrates by pulsed laser deposition. ZnO nanowires were formed on substrates by tube furnace. Shape and density of the ZnO nanowires were investigated by field emission scanning electron microscope. Average surface roughness and root mean square surface roughness were measure by atomic force microscope. Optical properties were investigated by Photoluminescence measurement. Density of ZnO nanowires grown on a-, c- and m-plane oriented 4H-SiC substrates were 17.89 μm-2, 9.98 μm-2 and 2.61 μm-2, respectively.

In this work, local oxidation behavior in phosphorous ion-implanted 4H-SiC has been investigated by using atomic force microscopy (AFM). The AFM-local oxidation (AFM-LO) has been performed on the implanted samples, with and without activation anneal, using an applied bias (~25 V). It has been clearly shown that the post-implantation annealing process at 1,650℃ has a great impact on the local oxidation rate by electrically activating the dopants and by modulating the surface roughness. In addition, the composition of resulting oxides changes depending on the doping level of SiC surfaces.

The morphology of etch pits in commercial 4H-SiC epi-wafer were investigated by molten-KOH etching. The etching process was optimized in 525~570℃ at 2~10 min and the novel type of etch pits was revealed. This type of etch pits have been considered as TED (threading edge dislocation) II, its origin and nature, however, are not reported yet. In this work, the morphology and evolution of etch pits during epitaxial growth were analyzed and the different behavior between TED and TEDII was discussed.

In this study, SiC single-crystal ingots were prepared on two seed crystals with different doping level by using the physical vapor transport (PVT) technique; then, SiC crystal wafers sliced from the grown SiC ingot were systematically investigated to find the effect of seed doping level on the doping concentration and crystal quality of the SiC. To exclude extra effects induced by adjustment of the process parameters, we simultaneously grew the SiC crystals on two seed crystals with different level, which were fabricated from previous two SiC crystal ingots.