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"TCAD Simulation"

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"TCAD Simulation"

Doping Optimization of 2.4 kV 4H-SiC Planar MOSFETs for Enhanced Electrical Performance
Taeyeong Yoon, Jeongmin Kim, Jun Lee, Songye Lim, Hyeondo Kang, Seung-hyun Park, Sang-mo Koo
J Electr Electron Mater 2025;38(6):672-676.   Published online November 1, 2025
DOI: https://doi.org/10.4313/JEEM.2025.38.6.10
Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 1017 to 6 × 1017 cm-3) and JFET regions (from 1 × 1016 to 7 × 1016 cm-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 1017 cm-3 and 5.3 × 1017 cm-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 1017 cm-3 and 1.5 × 1016 cm-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm2 and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 1017 cm-3 and 5.0 × 1016 cm-3, the Ron,sp was reduced to 1.31 mΩ·cm2 while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.
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A Study on the Corner Effect of Fin-type SONOS Flash Memory Using TCAD Simulation
Seung Dong Yang, Jae Sub Oh, Ho Jin Yun, Kwang Seok Jeong, Yu Mi Kim, Sang Youl Lee, Hee Deok Lee, Ga Won Lee
J Electr Electron Mater 2012;25(2):100-104.   Published online February 1, 2012
Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.
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