The quench behavior of wires for superconducting fault current limiters at DC faults was simulated, with a focus on the effect of capacitor discharge on the quench. The behavior was also expressed in mathematical forms to facilitate a better understanding of the simulation results and for rough analytical estimations of the wire length suitable for the circuit voltage and capacitance. The quench resistance development behavior for various wire lengths and circuit capacitances was simulated using the model developed in the previous work. The quench behavior was expressed in mathematical forms, reflecting the concept of heat balance. During the quench, the wire temperature increased more slowly for longer wires, but was found to increase in a similar pattern. The wire length estimated by the mathematical formula was close to the one obtained by the simulation, with an error range of a few %. The calculations will be used to estimate effectively the length of wires needed to build superconducting fault current limiters for applications in DC power systems.

Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

The quench behavior of coated conductors (CCs) was simulated with a focus on the initial stage of quenches, and the current limiting behavior of superconducting fault current limiters (SFCLs) at DC faults was calculated. Since the fault current reaches the peak in several ms in DC lines due to capacitor discharge, it is necessary to understand the initial quench behavior well. Considered in the simulation are characteristics of CCs in the flux-flow state, current sharing, non-uniform critical current distribution in CCs, and heat transfer to surroundings. The simulation fit data well. Using the CC model developed in the simulation, the current limiting behavior of SFCLs made of CCs at DC faults was calculated. Critical current distribution and heat transfer were found to affect the current limiting behavior of SFCLs less at DC faults. The calculation will contribute to the effective design of SFCLs for applications in DC lines.

Titanium dioxide (TiO₂) holds significant scientific and technological relevance as a key photocatalyst and resistive random-access memory, demonstrating unique physicochemical properties and serving as an n-type semiconductor. Understanding the density and arrangement of oxygen vacancies (VOs) is crucial for tailoring TiO₂’s properties to diverse technological needs, driving increased interest in exploring oxygen vacancy complexes and superstructures. In this mini review, we summarize the recent understandings of the fundamental properties of oxygen vacancies in bulk rutile (R-TiO₂) and anatase (A-TiO₂) based on DFT and beyond method. We specifically focus on the excess electrons and their spatial arrangement of disordered single VO in bulk R and A-TiO₂, aligned with the experimental findings. We also highlight the theoretical works on investigating the geometries and stabilities of ordered VOs complexes in bulk TiO₂. This comprehensive review provides insights into the fundamental properties of excess electrons in reduced TiO₂, offering valuable perspectives for future research and technological advancements in TiO₂-based devices.

By introducing curing kinetics and chemo-rheology for the epoxy resin formulation for ultra-high voltage gas insulated switchgear (GIS) Insulating Spacers, a study was conducted to simulate the curing behavior, flow and warpage analysis for optimization of the molding process in automatic pressure gelation. The curing rate equation and chemo-rheology equation were set as fixed values for various factors and other physical property values, and the APG molding process conditions were entered into the Moldflow software to perform optimization numerical simulations of the three-phase insulating spacer. Changes in curing shrinkage according to pack pressure were observed under the optimized process conditions. As a result, it was confirmed that the residence time in the solid state was shortened due to the lowest curing reaction when the curing holding pressure was 3 bar, and the occurrence of deformation due to internal residual stress was minimized.

In the past, the efficiency of solar cells had been increased in order to increase the efficiency of solar modules. However, in recent years, in order to increase output in the solar industry and market, the competitiveness of solar cells based on large-area solar cells and multi-bus bar has been increasing. Multi-busbar solar module is a technology to reduce power loss by increasing the number and width of the front busbar of the solar cell and reducing the current value delivered by the busbar by half through half-cutting. In the case of the existing M2 (156.75×156.75 ㎟) solar cell, even with a half-cut, power loss could be sufficiently reduced, but as the area of the solar cell is enlarged to more than M6 (166×166 ㎟), the need for more divisions emerged. This affected not only solar cells but also inverters required for module array configuration. Therefore, in this study, the electrical characteristics of a large-area solar cell and after division were extracted using Griddler simulation. The output characteristics of the module were predicted by applying the solar cell parameters after division to PSPice, and a guideline for the large-area solar module design was presented according to the number of divisions of the large-area solar cell.

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

Numerical simulation is a good way to predict the conversion efficiency of solar cells without a direct experimentation and to achieve low cost and high efficiency through optimizing each step of solar cell fabrication. TOPCon industrial solar cells fabricated with n-type silicon wafers on a larger area have achieved a higher efficiency than p-type TOPCon solar cells. Electrical and optical losses of the front surface are the main factors limiting the efficiency of the solar cell. In this work, an optimization of boron-doped emitter surface and front electrodes through numerical simulation using “Griddler” is reported. Through the analysis of the results of simulation, it was confirmed that the emitter sheet resistance of 150 Ω/sq along the front electrodes having a finger width of 20 μm, and the number of finger lines ~130 for silicon wafer of M6 size is an optimized technology for the front emitter surface of the n-type TOPCon solar cells that can be developed.

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

Injection molding is used in many industrial fields such as home appliances, vehicle parts, and electronic device parts because various resins can be molded, leading to mass production of complex shapes. Generally, the empirical prediction method is used to set the initial processing conditions of injection molding. However, this approach requires a lot of cost and its presented solution is not accurate. In this paper, injection molding was simulated through the Moldflow^TM in order to manufacture the spacer for gas insulated switch. Through the simulation, the flow of the resin with respect to the diameter of the inlet was analyzed. It was found that the process was possible at a higher resin temperature as the diameter of the inlet increased. In addition, through thermal analysis during injection of the resin, it was confirmed that a stagnation phenomenon occurred at the insert portion during injection molding, and the temperature of the resin was higher than that of the mold. As in this paper, if the spacer is manufactured by optimizing the injection hole and the temperature of the injection process based on simulation, it is expected that the spacer can be manufactured with high productivity.

Micro-LEDs can be applied to various parts of a product. However, it has disadvantages compared to general LEDs in large displays such as low efficiency, intensity, and contrast ratio, among others, owing to their short history of study. The simulations were carried out using ray-tracing software to investigate the change in light intensity and light distribution according to pattern shapes on the sapphire substrate of the flip-chip micro-LED (FC μ-LED) array. Three patterns-concave square patterns, convex square patterns, and Ag coated convex patterns-which existed on the opposite side of FC μ-LEDs (115 ㎛ × 115 ㎛) array, were applied. The intensity of FC μ-LEDs on the center of the receivers depends on the pattern depth with shape. The concave square patterns having FC μ-LEDs arrays show that decreasing intensity as the patterns depth. On the contrary, the convex square patterns having FC μ-LEDs arrays shows that increasing intensity as the patterns depth. In addition, the highest intensity shows that FC μ-LEDs having Ag-coated convex patterns on the opposite side of sapphire lead to a reduction in light crosstalk owing to the Ag film.

In this study, the physical mechanism and diffusion effects in aluminium implanted silicon was investigated. For fabricating power semiconductor devices, an aluminum implantation can be used as an emitter and a long drift region in a power diode, transistor, and thyristor. Thermal treatment with O₂ gas exhibited to a remarkably deeper profile than inert gas with N₂ in the depth of junction structure. The redistribution of aluminum implanted through via thermal annealing exhibited oxidation-enhanced diffusion in comparison with inert gas atmosphere. To investigate doping distribution for implantation and diffusion experiments, spreading resistance and secondary ion mass spectrometer tools were used for the measurements. For the deep-junction structure of these experiments, aluminum implantation and diffusion exhibited a junction depth around 20 μm for the fabrication of power silicon devices.

Atmospheric environmental problems have a major impact on human health and lifestyle. In humans, inhalation of nitrogen oxides causes respiratory diseases, such as bronchitis. In this paper, thermal analysis of a gas sensor was carried out to design and fabricate a wearable nylon-yarn gas sensor for the detection of NO_x gas. In the thermal analysis method, the thermal diffusion process was analyzed while operating the sensors at 40 and 60℃ to secure a temperature range that does not cause thermal runaway due to temperature in the operating environment. Thermal diffusion analysis was performed using the COMSOL software. The thermal analysis results could be useful for analyzing gas adsorption and desorption, as well as the design of gas sensors. The thermal energy diffusion rate increased slightly from 10.05 to 10.1 K/mm as the sensor temperature increased from 40 to 60℃. It was concluded that the sensor could be operated in this temperature range without thermal breakdown.

In order to fabricate high-quality SiC substrates for power electronic devices, various single crystal growing methods were prepared. These include the physical vapor transport (PVT) and top seeded solution growth (TSSG) methods. All the suggested SiC growth methods generally use induction-heating furnaces. The temperature distribution in this system can be easily adjusted by changing the hot-zone design. Moreover, precise temperature control in the induction-heating furnace is favorably required to grow a high-quality crystal. Therefore, in this study, we analyzed the heat transfer in these furnaces to grow SiC crystals. As the growth temperature of SiC crystals is very high, we evaluated the effect of radiation heat transfer on the temperature distribution in induction-heating furnaces. Based on our simulation results, a heat transfer strategy that controls the radiation heat transfer was suggested to obtain the optimal temperature distribution in the PVT and TSSG methods.

A shingled PV module is manufactured by dividing and bonding. In this method, the solar cell is divided by lasers and bonded using electrically conductive adhesives (ECAs). Consequently, the manufacturing cost increases because a process step is added. Therefore, we aim to reduce the production cost by reducing the amount of Ag paste used in the solar cell front. Various electrode structures were designed and simulated. The number of fingers was optimized by designing thinner fingers, and the number of fingers with the maximum power conversion efficiency was confirmed. The simulation confirmed the maximum efficiency in the 4-divided electrode pattern. The amount of Ag paste used for each electrode pattern was calculated and analyzed. The number of fingers was optimized by decreasing the width of the finger; this will not only reduce the amount of Ag paste required but also the increase the efficiency.

Micro-LEDs show lower efficiencies compared to general LEDs having large areas. Simulations were carried out using ray-tracing software to investigate the change in light extraction efficiency and light distribution according to chip-size of blue flip-chip micro-LEDs (FC μ-LEDs). After fixing the height of the square FC μ-LED chip at 158 μm, the length of one side was varied, with dimensions of 2, 5, 10, 30, 50, 100, 300, and 500 μm. The highest light-extraction efficiency was obtained at 10 μm, beyond which the efficiency decreased as the chip-size increased. The chip size-dependence of the FC μ-LEDs both without the patterned sapphire substrate, as well as vertical FC μ-LEDs, were analyzed.

For the investigation of dopant profiles in implanted Si_1-xGe_x, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in Si_1-xGe_x are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of R_p and 1.8% deviations of ΔR_p owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of R_p and 8.1% deviations of ΔR_p in the arsenic implanted Si_0.2Ge_0.8 layer and 8.5% deviations of R_p and 38% deviations of ΔR_p in the Si_0.5Ge_0.5 layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the Si_1-xGe_x layer becomes more important for accurate device scaling and fabrication technologies.

The shingled photovoltaic module can be produced by joining divided solar cells into a string of busbarless structure and arranging them in series and parallel to produce a module, in order to produce a high output per unit area. This paper reports a study to optimize solar cell electrode structure for shingled photovoltaic module fabrication. The characteristics of each electrode structure were analyzed according to the simulation program as follow: 80.62% fill factor in the six-junction solar cell electrode structure and 19.23% efficiency in the five-junction electrode structure. Therefore, the split electrode structure optimized for high-density and high-output shingled module fabrication is the five-junction solar cell electrode structure.

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

Current progress in the development of semiconductor technology in applications involving high electron mobility transistors (HEMT) and power devices is hindered by the lack of adequate ways todissipate heat generated during device operation. Concurrently, electronic devices that use gallium nitride (GaN) substrates do not perform well, because of the poor heat dissipation of the substrate. Suggested alternatives for overcoming these limitations include integration of high thermal conductivity material like diamond near the active device areas. This study will address a critical development in the art of GaN on diamond (GOD) structure by designing for ideal heat dissipation, in order to create apathway with the least thermal resistance and to improve the overall ease of integrating diamond heat spreaders into future electronic devices. This research has been carried out by means of heat transfer simulation, which has been successfully demonstrated by a finite-element method.

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, BF2 and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with C++ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

Thermal characteristics of 20 W LED module on light thermal conductive plastic (TCP) heat sink were investigated in comparison with that on aluminum die casting alloy (ADC-12). Thermal simulations of the heat sinks were conducted by using flow simulation of SolidWorks with the following input parameters: density is 1.70 and 2.82 kg/㎡, thermal conductivity is 20 and 92 W/(m·K) for TCP and ADC-12, respectively. The simulated and measured temperatures of the LED modules on TCP heat sink were consistent with its measured temperature, which was 3℃ higher that on ADC-12. The fabricated LED module on TCP heat sink with a weight of 120.5 g was 30% lighter in weight than that of the ADC-12 reference with 171.0 g.

Although there are existing Residual Current Protective Device (RCD) including detect electric leakage and elements such as short circuit and surge, the occurrence of incidents caused by electric faults, including fire, are still constant. The purpose of this study is to analyze the causes of accidents through the electric field distribution in the interpretation of the fault contact breaker. Simulation results by the arc fault has shown the convergence of temperature and electric field to the defect. Through their simulation results, the main cause of erosion phenomena in circuit breaker bar is the electric arc by concentration of electric field not due to dissolve by temperature.

In this paper, various heat dissipation designs for a rail anchoring failure detection module were investigated by a thermal flow analysis. For the detection module with the heat dissipation design on the overall housing surface, an average temperature inside the module was lowered by 25℃ when compared to no heat dissipation design. In addition, an internal heat-flow blocking layer and an heat conduction layer inserted between the LED module and housing case were effective in reducing the temperature in the rail anchoring failure detection, which has a limited space for installation and little air flow. Especially, the temperature near LED module decreased below 55℃ when the optimal heat dissipation design was applied.

For the formation of N+ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a SiO2/Si is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert N2gas and dry oxidation.

A vacuum Interrupter (VI), a core part that composes the breaking part of medium-voltage vacuum circuit breaker (VCB), has the excellent insulation performance and arc-extinguishing capability. SF6 gas had been used for the external insulation of VIs since the dielectric strength of SF6 gas is superior to that of other insulation gases. However, because of environmental problems related with global warming, a solid-insulated technology was recently researched. The functionally graded material (FGM), as changing spatially the distribution of the relative permittivity inside an insulator, can reduce the electric field stress at the specific region. Especially, the external insulation performance of the VI with the molded FGM insulator is greatly improved as compared with that of the existing VI or the VI with a new external shield. In this paper, the effectiveness of this FGM insulator is verified by the numerical simulation.

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

In this study, the change of optical characteristics was studied according to the micro optical pattern provided by photo lithography followed by thermal reflow process. The shape and luminance variation with micro pattern was evaluated by SEM and spectrometers. Also, we analyzed the luminance characteristics using the 3D-optical simulation (Optis works) program. As a result, we found that the radius of curvature(R) in micro pattern is decreased up to 77%(150℃) compared to the radius of curvature at the condition 100℃, which is caused by efficient reflow of organic material without chemical changes. The highest enhancement of brightness with optimum micro pattern was obtained at the condition of 120℃ reflow process. The brightness gain with optical micro patterns is more than 15% at the condition of R=16.95 um, θ =77.14° compared to original optical source. The results of light simulation with various radius of curvature and side angle of pattern shows the similar result of experiment evaluation of light behavior on optical micro patterns. It is regarded that the more effect on light enhancement was contributed by side angle which is effective factor on light reflection, rather than the curvature of micro-patterns.