With the rapid expansion of electric vehicles (EVs) and energy storage systems (ESS), ensuring the operational safety of lithium-ion batteries has become a critical technical challenge. Conventional battery management systems (BMS) primarily rely on threshold-based rule logic, which is limited in detecting coupled anomalies and early-stage degradation patterns. In this study, a deep learning-based framework for multivariate anomaly detection is proposed using BMS sensor data, including voltage, current, temperature, state of charge (SOC), and state of health (SOH). Five representative fault scenarios were defined, including thermal runaway precursors, cell voltage imbalance, SOC inconsistency, internal resistance increase, and communication delay. The proposed CNN-LSTM model was compared with conventional Rule-based methods and machine learning models, including Isolation Forest, Autoencoder, and LSTM. Experimental results show that the proposed model achieved the highest performance, with an F1-score of 0.885, an AUC of 0.94, and a detection delay of 8.1 s. In contrast, the Rule-based method exhibited a significantly higher false negative rate of 42.0%, indicating limitations in detecting complex anomaly patterns. These results demonstrate that the proposed spatiotemporal deep learning approach can significantly improve the accuracy and responsiveness of battery anomaly detection. Furthermore, the proposed method is expected to contribute to enhancing safety, reliability, and predictive diagnostics in next-generation intelligent BMS platforms.

Organic solar cells based on bulk heterojunction (BHJ) structures have attracted considerable attention because of their low fabrication cost, mechanical flexibility, and compatibility with solution-processing techniques. In BHJ organic photovoltaic devices, nanoscale morphology and crystallinity of the photoactive layer critically influence photovoltaic performance. In this study, the effects of solvent selection and thermal annealing on crystallization evolution and photovoltaic characteristics of P3HT:PCBM organic solar cells were systematically investigated. Three different solvents, including toluene, chlorobenzene (CB), and dichlorobenzene (DCB), were employed for active-layer fabrication, followed by post-thermal annealing treatment. UV–visible absorption spectroscopy revealed solvent-dependent differences in molecular ordering and intermolecular π–π interactions within the active layer. X-ray diffraction analysis confirmed that thermal annealing significantly enhanced crystallinity and lamellar ordering of P3HT domains, particularly for CB-processed films. Electrical characterization demonstrated that solvent evaporation behavior strongly affects photovoltaic performance. Among the investigated devices, the thermally annealed CB-processed device exhibited the highest power conversion efficiency of 1.83% with an enhanced short-circuit current density of 7.057 mA cm⁻². The improved device performance is attributed to optimized crystallization behavior and balanced nanoscale phase separation induced by the moderate evaporation characteristics of CB. In contrast, although DCB-assisted films exhibited relatively strong optical absorption and enhanced crystallinity, excessively slow solvent evaporation likely induced excessive aggregation and coarse phase separation, limiting efficient photovoltaic characteristics. These results demonstrate that solvent engineering combined with thermal annealing is an effective strategy for controlling morphology evolution and crystallization behavior in P3HT:PCBM bulk heterojunction solar cells.

GaN nanowire (NW)-based hybrid structures have attracted attention for optoelectronic applications due to their high surface area and efficient carrier transport. However, the optical transparency of GaN NWs is often limited by unintended residual species accumulated on the surface and in the inter-wire regions, as well as defect-related absorption, leading to reduced light transmission. In this work, we demonstrate that thermal annealing significantly improves the optical transparency of GaN NWs grown on indium tin oxide (ITO)/glass substrates. The transmittance increased from 47.9% to 78.5% at 550 nm after rapid thermal annealing at 800^oC for 3 min, while a comparable value (~75.5%) was achieved at 600^oC for 5 min. PbBr₃ was deposited onto the GaN NWs to form hybrid structures, and temperature-dependent photoluminescence (TDPL) measurements revealed enhanced emission stability with suppressed peak shift and reduced spectral broadening. Arrhenius analysis based on a two-channel model revealed that the activation energy of the dominant non-radiative recombination pathway increased from 62 meV in the as-grown sample to 85 meV after thermal annealing, while its relative contribution remained nearly unchanged. In contrast, the shallow trap-assisted pathway exhibited a similar activation energy of approximately 6 meV in both samples, but its contribution decreased from 0.35 to 0.17 after annealing. As a result, the internal quantum efficiency (IQE) improved from 75.9% to 87.4%. These results show that thermal annealing improves optical transparency by removing residuals and suppresses defect-related recombination, leading to enhanced carrier dynamics and improved optical performance of PbBr₃-based hybrid structures.

The continuous rise of atmospheric carbon dioxide (CO₂) emissions highlights the urgent need for sustainable air purification technologies. Current Direct Air Capture (DAC) filters often rely on toxic amines, which limit long-term stability and safe application. Here, we report a non-toxic PAN-based nanofiber air filter fabricated by electrospinning and urea-assisted carbonization. Structural analyses confirmed the introduction of nitrogen functionalities that enhanced CO₂ affinity, while SEM and FT-IR revealed graphitic carbon formation. In air-chamber tests, the optimized carbonized nanofiber reduced CO₂ concentration from 25,000 ppm to 2,000 ppm, a level generally regarded as acceptable for indoor environments, while simultaneously removing over 95% of PM₁₀, PM_2.5, and PM_0.1 particulates. This dual functionality, combined with facile fabrication and material safety, demonstrates strong potential for PAN-derived carbon nanofiber membranes in DAC systems and eco-friendly air purification devices. These findings suggest a viable pathway toward scalable, sustainable air-filter technologies for carbon-neutral applications.

e investigated the effects of post-annealing in vacuum, nitrogen, and hydrogen atmospheres on the structural, electrical, and optical properties of 600 nm thick Al-doped ZnO (ZnO:Al) thin films deposited by RF magnetron sputtering at room temperature. Post-annealing in hydrogen atmosphere at 400℃ for 1 hour showed the most significant improvement in electrical properties. Resistivity decreased from 9.11×10⁻³ to 1.4×10⁻³ Ω·cm, electron mobility increased from 4.11 to 18.23 cm²/V·s, and electron carrier concentration increased from 1.63×10²⁰ to 4.85×10²⁰ cm⁻³. In contrast, post-annealing in vacuum and nitrogen atmospheres resulted in degraded electrical properties due to oxygen and nitrogen chemisorption at grain boundaries. The enhancement in hydrogen-annealed films was attributed to the formation of additional oxygen vacancies and desorption of adsorbed oxygen species from grain boundaries. All films maintained excellent optical transparency of 80-90% in the visible range. The optical bandgap exhibited a blue-shift from 3.365 eV to 3.624 eV due to the Burstein-Moss effect induced by the increased electron carrier concentration. These results confirmed that hydrogen atmosphere post-annealing is the most effective method for enhancing the electrical conductivity of ZnO:Al thin films while maintaining high optical transparency.

In this study, Y₂O₃ thin films were deposited on Si(100) wafers using an RF sputtering system with a Y₂O₃ target. The Y₂O₃ thin film was confirmed to have a thickness of 227 nm/min and a uniformity of 1.34% at a substrate temperature of 400℃. All samples were annealed at 600, 800, and 1,000℃ for 1 hour in an O₂ gas atmosphere using the furnace. The analysis of the XRD patterns revealed that the peak intensity increased with annealing up to 800℃, but decreased when the annealing temperature was raised to 1,000℃. The XPS analysis confirmed the onset of crystallization at 800℃, in agreement with the trends observed in the XRD results. According to the AFM results, the surface became slightly smoother after heat treatment, as indicated by a reduced RMS roughness of approximately 1.792 nm.

With the advancement of the information society, the demand for highly integrated and multi-functional electronic devices is rapidly increasing. To meet these demands, high-performance transistors with low power consumption, high-speed operating, and mechanical flexibility are essential. Among various candidates, semiconducting single-walled carbon nanotubes (s-SWCNT)-based transistors, which exhibit intrinsically ambipolar characteristics, have emerged as promising components for CMOS-like circuits. In this study, s-SWCNT were selectively dispersed using rr-P3DDT, a thiophene-based conjugated polymer, and filed-effect transistors (FETs) were fabricated by inducting directional alignment for enhanced charge transport through an off-centered spin-coating process. The electrical characteristics of the fabricated s-SWCNT FETs were evaluated under various thermal annealing conditions (100℃, 150℃, 200℃, and 250℃). Off-centered spin-coated and high temperature annealed s- SWCNT FETs exhibited high field-effect mobilities over 5 cm²/Vs in both p-type and n-type operation, along with ideal Vshaped ambipolar transfer curves. These results indicate a significant enhancement in ambipolar performance due to efficient desorption of residual oxygen and water molecules in active channel via high temperature annealing. Furthermore, CMOS-like inverter circuits demonstrated an ideal inversion voltage (VIN = V_DD/2) and a high voltage gain of approximately 9.5. These findings highlight the potential of SWCNT-based materials for realizing next-generation flexible electronic circuits that combine high-performance, energy efficiency, and simplified solution-processing.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Recently, oxide semiconductors have assumed a pivotal role in electronic displays and transparent electronic devices such as amorphous indium gallium zinc oxide (a-IGZO), characterized by high electron mobility and excellent stability. a- IGZO is very suitable for next-generation applications such as flexible displays because it is possible to manufacture highperformance transistors even at low temperatures. However, since the electrical properties tend to deteriorate in hightemperature environments, research aimed at improving thermal stability is needed. In this study, a low-temperature plasma annealing process was introduced to improve the high-temperature stability of the a-IGZO thin film. This process enhances electron mobility by reducing defects in the a-IGZO film and provides stable device performance even under high-temperature conditions. As a result of the experiments of 5 min, 10 min, 15 min, and 20 min, the a-IGZO TFT, which was subjected to plasma annealing at 160℃ for 5 min, showed the best electrical performance, especially in charge mobility and current-voltage characteristics. The technical potential for improving the performance of a-IGZO-based display device was emphasized, and the foundation for applying this power generation to flexible displays and next-generation electronic devices was laid. Future research will focus on determining the optimal annealing conditions by exploring various temperature ranges and plasma parameters to integrate these results into the actual device manufacturing process. These efforts are expected advance significantly to advancing next-generation high-performance display technology.

Neuromorphic computing, inspired by the biological mechanisms of neural signal transmission, has emerged as a promising technology for efficient and parallel data processing with minimal power consumption. In this study, we developed floating-gate organic thin-film transistors (OTFTs) with self-assembled monolayer (SAM)-based tunneling layers to mimic the characteristics of artificial synapses. The tunneling layers were formed using mixed phosphonic acid SAMs with varying ratios of octadecylphosphonic acid (ODPA) and 12-pentafluorophenoxydodecylphosphonic acid (PFPA). The influence of these ratios on the memory and neuromorphic characteristics of the devices was systematically evaluated. Our results revealed that the ODPA ratio significantly impacts the hysteresis window, with higher ODPA content yielding improved memory characteristics. Conversely, the PFPA : ODPA ratio of 2:1 exhibited the lowest non-linearity (NL = 0.48), demonstrating the potential for highly accurate weight updates in neuromorphic devices. Additionally, pulse width modulation studies showed that a pulse width of 100 ms optimized the linearity and stability of long-term potentiation (LTP) and depression (LTD) characteristics. The combination of sol-gel processed AlOx as a floating-gate layer and tailored SAM-based tunneling layers allowed for precise control of device performance. These findings highlight the importance of molecular engineering in designing SAM layers to balance memory retention and neuromorphic functionality. This study provides a pathway for advancing organic floating-gate transistors as a core component in next-generation neuromorphic computing systems.

The solution-based fabrication process for resistive random-access memory (ReRAM) offers several advantages over conventional vapor deposition processes, including simplicity, cost-effectiveness, and high versatility for coating complex structures over large areas. In this study, a TiO₂-based ReRAM device was fabricated using a solution process with Pt top and P⁺⁺-Si bottom electrodes. The synthesized TiO₂ films contain a residual Cl element as revealed by X-ray photoelectron spectroscopy (XPS). Reversible volatile resistance switching was observed due to the formation of conductive Ti-O-Ti networks in the TiO₂ layer. Post-annealing led to an increase in the threshold voltage (Vth). Asymmetric Current-Voltage characteristics was observed due to the different in the work functions of the electrodes. Additionally, the influence of compliance current settings on filament formation and hysteresis behavior was systematically investigated. The results demonstrated that higher compliance currents enhanced the hysteresis width for both positive and negative voltage bias conditions.

In parallel with the efforts to improve the device performance in modern integrated circuits, it is necessary to downscale their core components, field-effect transistors (FETs), generally gauged by their physical gate length. Upon such device scaling, the emergence of the short-channel effect impedes further scaling into the nanometer scale in the silicon VLSI (Very-Large-Scale-Integration) system. To address this issue, two-dimensional (2D) semiconductors, leveraging their atomically thin thickness and dangling-bond-free characteristics, are being highlighted as a material solution for future scaling technology without severe mobility degradation. Despite the expected ideal physical properties, 2D semiconductors have yet to realize their full potential owing to the limited development of integration technology. In this context, we survey and review the tailored van der Waals integration technologies for 2D FETs. In particular, we provide an in-depth study of both van der Waals integrated contact and dielectric methods along with an explanation of customized materials. In essence, this van der Waals integrationcentered approach will be a core strategy to implement the high-performance 2D transistors that meet the demand of FET miniaturization.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

We propose a real-time information propagation arithmetic neural network (PANN) that minimizes the loss of power generation output of the system in the event of sudden changes in the module due to strong external typhoons or earthquakes at the solar power generation facility site. In addition, we propose a new double-sided module reflector that can reduce the local loss of power generation efficiency of the single-sided module reflector that is currently widely distributed, as well as the environmental pollution and inconvenience of maintenance work of the existing double-sided module. We present a computational network that can detect the faulty solar panel in real-time by checking the fault status of the installed solar panel and using a real-time computation method through a node-to-node diffusion method. In particular, this method recognizes the power loss part due to sudden changes in the module in real time and can take emergency measures for various nonlinear field facilities through a neural structure that finds the optimal distance up, down, left, and right. To confirm the characteristics of the loss reduction control of the field facility, we confirmed that the system was configured as a 7-degree-of-freedom control model using the PANN neural network learning structure method and improved the power generation output. PANN (Propagation Arithmetic Neural Networks) and various module systems are proposed for the real-time recovery of faulty solar panels and improving module system efficiency.

In this study, Pb(Ni_1/3Nb_2/3)O₃-Pb(Zr,Ti)O₃ ceramics substituted with Pb(Mg_1/2W_1/2)O₃ were fabricated with the variation of CuO for application to ultrasonic cleaning of removable orthodontic appliances (ROA). And their piezoelectric and dielectric properties were investigated. At the 0.12 wt% CuO added ceramics sintered at 930℃, the excellent values of dielectric constant=2,519, density=7.82 g/㎤, kp=0.64, d₃₃=536 pC/N, Qm=57 were obtained, respectively. These values were suitable for application to ultrasonic cleaning of ROA.

The display industry has recently been at the forefront of innovative advancements in modern electronic devices. Technological progress such as flexible display holds significant potential across various application fields, particularly in wearable devices and rollable displays. A low-temperature process is essential for fabricating such displays. One of the key technologies in displays is the thin film transistor (TFT), with amorphous indium gallium zinc oxide (a-IGZO) receiving particular attention. a-IGZO is widely applied in high-performance displays due to its high charge mobility and stability. While a thermal treatment above 350℃ is typically required to maximize the electrical performance of a-IGZO TFTs, such high temperatures pose challenges for utilizing polymer substrates like plastics. Here, we thesis investigates the simultaneous lowtemperature plasma annealing process to develop next-generation high-performance flexible display devices. To define the optimal temperature, devices were fabricated and analyzed at varying temperatures of 40℃, 80℃, 120℃, and 160℃. Experimental results indicated that devices fabricated at 160℃ and 80℃ exhibited superior performance, with those at 160℃ demonstrating better performance in terms of current ratio, threshold voltage, and subthreshold swing. These findings confirm that the simultaneous low-temperature plasma annealing process is effective for next-generation high-performance displays.

MBB (multi-busbar) technology is a module technology to achieve high power, and the use of a number of thin circular metal wires increases light-receiving capacity and reduces resistance. In the process of interconnection using a wire, the stress of the cell increases depending on the degree of coupling between the wire and the cell and the degree of damage caused by heat, or the mobility of current decreases due to poor bonding. The degree of such loss is affected by IR lamp, hot plate temperature and wire thickness. In addition, the values of contact resistance were compared and analyzed to analyze the cause of the decrease in electrical characteristics. In this study, process condition optimization was carried out through peeling test, SEM analysis, EL test, and pre/post bonding efficiency characteristic analysis of the bonded cell according to process conditions, compared the contact resistance.

Memristors, as next-generation memory devices, have garnered significant academic interest. Among them, TiO₂/TiO_2-x based memristors have particularly attracted substantial scholarly attention. Research on the activation and stability of TiO2 based memristor devices through process parameters is essential. Here, to determine the impact of process parameters on the activation of TiO₂/TiO_2-x based memristor devices, we fabricated the memristor devices using a sputtering system andconducted annealing at 400℃. Additionally, to analyze the electrical characteristics of the devices, we measured the I-V curves and C-V curves. Also, we examined TiO₂/TiO_2-x based memristor devices surface using SEM. Consequently, it was observed that the devices subjected to annealing exhibited improved hysteresis curves in the I-V characteristics, a reduced bandgap, and changes in resistance compared to the non-annealed devices. The retention test results further demonstrated that the set/reset characteristics of the devices were stable, confirming their potential applicability as memory devices.

The transparent electrode characteristics of the SnO₂/AgNi/SnO₂ (OMO) multilayer structures prepared by sputtering were investigated according to the annealing temperature. Ni-doped Ag of various compositions was selected as the metal layer and heat treatment was performed at 100~300℃ to evaluate the thermal stability of the metals. The manufactured OMO multilayer structures were heat treated for 6 hours at 400~600℃ in an N₂ atmosphere. The structural, electrical, and optical properties of the OMO structures before and after annealing were evaluated and analyzed using a UV-VIS spectrophotometer, 4-point probe, XPS, FE-SEM, etc. OMO with Ni-doped Ag shows improved performance due to the reduction of structural defects of Ag during annealing, but OMO structure with pure Ag shows degradation characteristics due to Ag diffusion into the oxide layer during high-temperature annealing. The figure of merit (FOM) of SnO₂/Ag/SnO₂ was highest at room temperature and gradually decreased as the heat treatment temperature increased. On the other hand, the FOM value of SnO₂/AgNi/SnO₂ mostly showed its maximum value at high temperature(~550℃). In particular, the FOM value of SnO₂/Ag-Ni (3.2 at%)/SnO₂ was estimated to be approximately 2.38×10^-2 Ω^-1. Compared to transparent electrodes made of other similar materials, the FOM value of the SnO₂/Ag-Ni (3.2 at%)/SnO₂ multilayer structure is competitive and is expected to be used as an alternative transparent conductive electrode in various devices.

This study investigates the post-thermal treatment effects on the efficiency of silicon heterojunction solar cells, specifically examining the influence of annealing on p-type microcrystalline silicon oxide and ITO thin films. By assessing changes in carrier concentration, mobility, resistivity, transmittance, and optical bandgap, we identified conditions that optimize these properties. Results reveal that appropriate annealing significantly enhances the fill factor and current density, leading to a notable improvement in overall solar cell efficiency. This research advances our understanding of thermal processing in siliconbased photovoltaics and provides valuable insights into the optimization of production techniques to maximize the performance of solar cells.

The polymer crystallization process, promoting the formation of ferroelectric β-phase, is essential for developing polyvinylidene fluoride (PVDF)-based high-performance piezoelectric energy harvesters. However, traditional high-temperature annealing is unsuitable for the manufacture of flexible piezoelectric devices due to the thermal damage to plastic components that occurs during the long processing times. In this study, we investigated the feasibility of introducing a flash lamp annealing that can rapidly induce the β-phase in the PVDF layer while avoiding device damage through selective heating. The flash lightirradiated PVDF films achieved a maximum β-phase content of 76.52% under an applied voltage of 300 V and an on-time of 1.5 ms, a higher fraction than that obtained through thermal annealing. The PVDF-based piezoelectric energy harvester with the optimized irradiation condition generates a stable output voltage of 0.23 V and a current of 102 nA under repeated bendings. These results demonstrate that flash lamp annealing can be an effective process for realizing the mass production of PVDF-based flexible electronics.

In this study, ITO thin films were fabricated on a glass substrate at different thicknesses without introducing oxygen using RF sputtering system. The structural, electrical, and optical properties were evaluated at various thicknesses ranging from 50 to 300 mm. As the thickness of deposited ITO thin film become thicker from 50 to 100 mm, carrier concentration, mobility, and band gap energy also increased while the resistivity and transmittance decreased in the visible light region. When the film thickness increased from 100 to 300 mm, the carrier concentration, mobility, and band gap energy decreased while the resistivity and transmittance increased. The optimum electrical properties were obtained for the ITO film 100 nm. After optimizing the thickness, the ITO thin films were post-annealed at different temperatures ranging from 100 to 300℃. As the annealing temperature increased, the ITO crystal phase became clearer and the grain size also increased. In particular, the ITO thin film annealed at 300℃ indicated high carrier concentration (4.32 × 10²¹ cm^-3), mobility (9.01 cm2/V·s) and low resistivity (6.22 × 10^-4 Ω·cm). This means that the optimal post-annealing temperature is 300℃ and this ITO thin film is suitable for use in solar cells and display application.

As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher chip density, thin-film layers have been deposited iteratively. The poor film uniformity resulting from deposition or chemical mechanical planarization (CMP) significantly affects chip yield. Therefore, the development of novel fabrication processes to enhance film uniformity is required. In this context, high-pressure deuterium annealing (HPDA) is proposed to reduce the surface roughness resulting from the CMP. The HPDA is carried out in a diluted deuterium atmosphere to achieve cost-effectiveness while maintaining high pressure. To confirm the effectiveness of HPDA, time-of-flight secondary-ion mass spectrometry (ToF-SIMS) and atomic force microscopy (AFM) are employed. It is confirmed that the absorbed deuterium gas facilitates the diffusion of silicon atoms, thereby reducing surface roughness.

Laser-induced plasmonic sintering of metal nanoparticles (NPs) holds significant promise as a technology for producing flexible conducting electrodes. This method offers immediate, straightforward, and scalable manufacturing approaches, eliminating the need for expensive facilities and intricate processes. Nevertheless, the metal NPs come at a high cost due to the intricate synthesis procedures required to ensure long-term reliability in terms of chemical stability and the prevention of NP aggregation. Herein, we induced the self-generation of metal nanoparticles from Ag organometallic ink, and fabricated highly conductive electrodes on flexible substrates through laser-assisted plasmonic annealing. To demonstrate the practicality of the fabricated flexible electrode, it was configured in a mesh pattern, realizing multi-touchable flexible touch screen panel.

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

The effects of the annealing temperature on the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films grown on quartz substrates by radio-frequency magnetron sputtering were investigated. The thin films were annealed at various annealing temperatures for 20 min in a rapid thermal annealer after growing the thin films. The experimental results showed that the annealing temperature has a significant effect on the properties of the SrWO₄:Sm³⁺ thin films. The crystal structure of the as-grown SrWO₄:Sm³⁺ thin films was transformed from amorphous to crystalline after annealing at 800℃. The preferred orientation along (112) plane and a significant increase in average grain size by 820 nm were observed with increasing the annealing temperature. The average optical transmittance in the wavelength range of 500~1,100 nm was decreased from 72.0% at 800℃ to 44.2% at an annealing temperature of 1,000℃, where the highest value in the photoluminescence intensity was obtained. In addition to the red-shift of absorption edge, a higher annealing temperature caused the optical band gap energy of the SrWO₄:Sm³⁺ thin films to fall rapidly. These results suggest that the structural, morphological, and luminescent properties of SrWO4:Sm3+ thin films can be controlled by varying annealing temperature.

The Ga₂O₃ thin films were deposited using an RF sputtering system and the effect of crystallographic and optical properties under rapid thermal annealing conditions on Ga₂O₃ thin film was evaluated. A rapid thermal annealing method can fabricate a crystalline Ga₂O₃ thin film which is applied to various fields with a low cost and a high efficiency compared with the conventional post-annealing method. In this study, the Ga₂O₃ treated at 900℃ for 1 min showed the beta and gamma phases in XRD measurement. In optical properties, the crystalline Ga₂O₃ represented a high transmittance of more than 80% in the visible region and was calculated with a high optical bandgap energy of 4.58 eV. The beta and gamma phases Ga₂O₃ can be obtained by adjusting the rapid thermal annealing temperatures, and the various properties such as the optical bandgap energy can be controlled. Moreover, it is expected that crystalline Ga₂O₃ can be applied to various devices by controlling not only temperature but process time.

Flash lamp annealing (FLA) of metal nanoparticle (NP) ink has provided powerful strategies to fabricate highperformance electrodes on a flexible substrate because of its rapid processing capability (in milliseconds), low-temperature process, and compatibility with to roll-to-roll process. However, metal NPs [e.g., gold (Au), silver (Ag), copper (Cu), etc.] have limitations such as difficulty in synthesizing fine metal NPs (diameter less than 10 nm), high price, and degradation during ink storage and FLA processing. In this regard, organometallic ink has been proposed as a material that can replace metal NPs due to their low-cost (usually 1/100 times cheaper than metal nano inks), low-temperature processability, and high material stability. Despite these advantages, the fabrication of flexible electrodes through FLA treatment of organometallic compounds has not been extensively researched. In this paper, we experimentally guide how to determine the optimal conditions for forming electrodes on flexible substrates by considering material parameters, and flashlight processing parameters (energy density, pulse duration, etc) to minimize the difficulties that may arise during the FLA of organometallic ink.

With the increasing demand for mobile devices featuring multi-touch operation, extensive research is being conducted on touch screen panel (TSP) Readout ICs (ROICs) that should possess low power consumption, compact chip size, and immunity to external noise. Therefore, this paper discusses capacitive touch sensors and their readout circuits, and it introduces research trends in various circuit designs that are robust against external noise sources. The recent state-of-the-art TSP ROICs have primarily focused on minimizing the impact of parasitic capacitance (Cp) caused by thin panel thickness. The large Cp can be effectively compensated using an area-efficient current compensator and Current Conveyor (CC), while a display noise reduction scheme utilizing a noise-antenna (NA) electrode significantly improves the signal-to-noise ratio (SNR). Based on these achievements, it is expected that future TSP ROICs will be capable of stable operation with thinner and flexible Touch Screen Panels (TSPs).

Multilayer Ceramic Capacitors (MLCCs) are essential passive components in the electronics industry, known for their high capacitance due to the multilayer structure comprising inner electrodes and dielectric layers. Nickel electrodes are commonly used in MLCCs as the inner electrodes, and to prevent oxidation during the co-firing of the dielectric layers with nickel electrodes, reducing atmosphere is required. However, reducing atmosphere sintering can also induce a reduction of the dielectric, necessitating precise control of oxygen partial pressure. To explore the possibility of using oxide electrodes that do not require reducing atmosphere sintering, we analyze the electrical properties of nickel oxide (NiO) as a potential candidate. As a preliminary study on its use as an alternative inner electrode, the correlation between microstructure and electrical properties of bulk NiO under different sintering conditions was investigated to gain insights into the conduction mechanisms of the material.