Silicon carbide (SiC) MOSFETs provide superior performance compared to traditional silicon devices under hightemperature and high-power conditions, making them particularly valuable for power electronics applications requiring highfrequency switching and high-energy efficiency. As the electric vehicle (EV) market expands, these devices are commonly packaged into six-pack modules, which can show their different electrical characteristics between the bare-die device and the package due to packaging that improves heat dissipation and other properties. This study uses bare-die SiC MOSFETs to explore their intrinsic characteristics and evaluate their performance in a half-bridge configuration. A half-bridge circuit was constructed, and performance was assessed by varying driving frequencies (10 kHz and 50 kHz) and adjusting the duty cycle between 20% and 80%. Analysis revealed that, at a fixed switching frequency, the average output voltage and average output current are proportional to the duty cycle.

Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

The 4H-SiC VDMOSFET demonstrates a high reverse breakdown voltage (BV) due to the JFET region but experiences relatively high on-resistance (R_on). A widely adopted method to reduce the R_on is to uniformly increase the doping concentration of the JFET region, which results in a trade-off that reduces the BV. This study proposes a method to optimize the segmentation of the JFET region by selectively increasing the doping concentration using ‘total doping’, ‘half-doping’, and ‘quarter-doping’. The optimized quarter segment with a specific doping concentration slightly reduces BV, but the sharp decrease in specific on-resistance (R_on,sp) results in a 105% improvement in the performance index, Baliga’s Figure of Merit (BFOM). This research suggests the potential for electrically superior designs by modifying the doping concentration in the JFET region of conventional VDMOSFET structures.

4H-Silicon carbide (4H-SiC) is a promising material for power and harsh environment devices owing to its superior material properties, including wide bandgap, high critical electric field, and high thermal conductivity. However, despite the advantages of 4H-SiC, its channel mobility is reduced due to the high interface defect density between SiC and the oxide film, leading to increased device switching loss. Therefore, it is necessary to develop new fabrication methods to improve the quality of the SiO₂/4H-SiC interface. According to recent research, the effect of high-temperature (1,250~1,300℃) nitric oxide (NO) annealing on the interface states of SiO₂/4H-SiC and the channel mobility of 4H-SiC metal-oxide-semiconductor-field-effect transistors (MOSFETs) were investigated. Previous studies have optimized the NO post-oxidation annealing (POA) process, using N₂ diluted NO at 1,300℃ to reduce the high SiO₂/4H-SiC interface trap density (D_it). This paper focuses on high-temperature (1,250℃) 10% NO annealing to reduce interface defects by integrating nitrogen atoms into the oxide layer near the SiC interface, potentially increasing the channel mobility. Electrical properties such as D_it, threshold voltage (V_th), field-effect mobility (μ_FE), and specific on-resistance (R_on,sp) were assessed through capacitance-voltage (C-V) and current-voltage (I-V) measurements. It has been confirmed that the interface defect density of the gate oxide film was effectively improved under the POA conditions of 10% NO for 1 hour at 1,250℃.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (Ron,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in Ron,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the Dit.

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

In this research, we evaluated the electrical properties of polycrystalline-gallium-oxide (Ga₂O₃) thin films grown by mist-CVD. A 500~800 nm-thick Ga₂O₃ film was used as a channel in a fabricated bottom-gate MOSFET device. The phase stability of the β-phase Ga₂O₃ layer was enhanced by an annealing treatment. A Ti/Al metal stack served as source and drain electrodes. Maximum drain current (I_D) exceeded 1 mA at a drain voltage (VD) of 20 V. Electron mobility of the β-Ga₂O₃ channel was determined from maximum transconductance (gm), as approximately, 1.39 cm²/Vs. Reasonable device characteristics were demonstrated, from measurement of drain current-gate voltage, for mist-CVD-grown Ga₂O³ thin films.

A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower RDS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys’ process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga’s figure of merit (~94.22 MW/cm²) than the symmetric structure (~46.93 MW/cm²), and the breakdown voltage of the device increases by approximately 70%.

In this study, MOSFETs fabricated on Si-doped, MBE-grown β-Ga₂O₃ are demonstrated. A Si-doped Ga₂O₃ epitaxial layer was grown on a Fe-doped, semi-insulating 1.5 cm × 1 cm Ga₂O₃ substrate using molecular beam epitaxy (MBE). The fabricated devices are circular type MOSFETs with a gate length of 3 μm, a source-drain spacing of 20 μm, and a gate width of 523 μm. The device exhibited a good pinch-off characteristic, a high on-off drain current ratio of approximately 2.7×10⁹, and a high breakdown voltage of 1,080 V, which demonstrates the potential of Ga₂O₃ for power device applications including electric vehicles, railways, and renewable energy.

In this work, we have investigated the effect of a 30-min thermal anneal at 550℃ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.

Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at 570℃ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above 500℃. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ø_min method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the I_d-V_g relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ø_min method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ø_min method and the TD method reflected the short-channel effect.

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from 10¹³ to 5×10¹⁵ cm^-2 was performed to dope the polycrystalline silicon gate layer. For implant doses of 10¹⁴/㎠ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of 10¹⁴/㎠ or less, which was attributed to the decreased gate current under the gate-depletion effects.

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was 32 ㎛. The doping concentration of floating island was 5 × 1,012 ㎠. And the width of floating island was 3 ㎛. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and 0.108 Ω㎠ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.

This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained 60㎛ N-drift layer depth, 791.29 V breakdown voltage, 0.248 Ω·cm2 on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package

This paper was proposed 900 V Power MOSFET with ESD protection circuits using zener diodes. And we were carried out and analyzed its electrical characteristics. As a result of designing 900 V power MOSFET, we obtained 1,000 V breakdown voltage, 3.49 V threshold voltage and 0.249 Ω·cm2. And we designed ESD circuits using 2 series zener diode and 4 series zener diodes. After analyzing electrical characteristics, we obtained 26 V forward voltage drop and 47 V breakdown voltage. Therefore, This devices can enoughly use power module, SMPS and Automotive.

Generally, MWCNT, with thermal, chemical and electrical superiority, is manufactured with CVD (Chemical Vapor Deposition). Using MWCNT, it is comonly used as gas sensor of MOS-FET structure. In this study, in order to repeatedly detect gases, the author had to effectively eliminate gases absorbed in a MWCNT sensor. So as to eliminate gases absorbed in a MWCNT sesor, the sensor was applied heat of 423[K], and in order to observe how the applied heat was diffused within the sensor, the author interpreted the diffusion process of heat, using COMSOL interpretation program. In order to interpret the diffusion process of heat, the author progressed modeling with the structure of MWCNT gas sensor in 2-dimension, and defining heat transfer velocity(u=△T/△χ), accorded to governing equation within the sensor, the author proposed heat transfer mechanism.

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[Ω], showing 10% improvement compared to the conventional MOSFET at 700[V].

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device, it is essential to increase its conductance. However, a trade-off relationship between the breakdown voltage and conductance of the device have been the critical difficulty to improve. In this paper, theoretical analysis of electrical benefits on single floating island power MOSFET is proposed. By the method, the optimization point has set defining the doping limit under single floating island structure. The numerical multiple 2.22 was obtained which indicates the doping limit of the original device, improving its ON state voltage drop by 45%.

This paper was analyzed electrical characteristics of super junction power MOSFETconsidering to charge imbalance. We extracted optimal design and process parameter at -15% of chargeimbalance. Considering extracted design and process parameters, we fabricated super junction MOSFETand analyzed electrical characteristics. We obtained 600∼650 V breakdown voltage, 224∼240 mΩ onresistance. This paper was showed superior on resistance of super junction MOSFET. We can use forautomobile industry.

This paper was showed latch up characteristics of super junction power MOSFET by parasiticthyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was 90°, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

In this paper, we analyze electrical characteristics of n/p-pillar layer according to trench anglewhich is the most important characteristics of SJ MOSFET and core process. Because research target is600 V class SJ MOSFET, so conclusively trench angle deduced 89.5 degree to implement the breakdownvoltage 750 V with 30% margin rate. we found that on resistance is 22 mohm·cm2 and threshold voltageis 3.5 V. Moreover, depletion layer of electric field distribution also uniformly distributes.