MoS₂ has attracted significant attention as a next-generation semiconductor material to overcome the physical scaling limits of silicon-based devices due to its atomic thinness and excellent electrical properties. However, high contact resistance and the formation of Schottky barriers resulting from interface defects during the metal deposition process remain major bottlenecks that degrade overall device performance and reliability. In this study, we fabricated MoS₂ FETs by employing Sb₂Te₃, van der Waals (vdW) contacts. Minimized interface inhomogeneity was achieved through a hemispherical stamp-based dry transfer of h-BN for device encapsulation. h-BN encapsulation decreased the hysteresis window in the ±25 V gate voltage range from 17 V to 11.5 V compared to un-capped devices, confirming that charge trapping phenomena induced by external environmental factors were suppressed. Consequently, the dry transfer technique of h-BN using a hemispherical stamp demonstrated in this study provides a potential solution for securing the long-term reliability of MoS₂ devices with vdW contact by minimizing interface contamination.

Silicon carbide (SiC) MOSFETs provide superior performance compared to traditional silicon devices under hightemperature and high-power conditions, making them particularly valuable for power electronics applications requiring highfrequency switching and high-energy efficiency. As the electric vehicle (EV) market expands, these devices are commonly packaged into six-pack modules, which can show their different electrical characteristics between the bare-die device and the package due to packaging that improves heat dissipation and other properties. This study uses bare-die SiC MOSFETs to explore their intrinsic characteristics and evaluate their performance in a half-bridge configuration. A half-bridge circuit was constructed, and performance was assessed by varying driving frequencies (10 kHz and 50 kHz) and adjusting the duty cycle between 20% and 80%. Analysis revealed that, at a fixed switching frequency, the average output voltage and average output current are proportional to the duty cycle.

Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

With the advancement of the information society, the demand for highly integrated and multi-functional electronic devices is rapidly increasing. To meet these demands, high-performance transistors with low power consumption, high-speed operating, and mechanical flexibility are essential. Among various candidates, semiconducting single-walled carbon nanotubes (s-SWCNT)-based transistors, which exhibit intrinsically ambipolar characteristics, have emerged as promising components for CMOS-like circuits. In this study, s-SWCNT were selectively dispersed using rr-P3DDT, a thiophene-based conjugated polymer, and filed-effect transistors (FETs) were fabricated by inducting directional alignment for enhanced charge transport through an off-centered spin-coating process. The electrical characteristics of the fabricated s-SWCNT FETs were evaluated under various thermal annealing conditions (100℃, 150℃, 200℃, and 250℃). Off-centered spin-coated and high temperature annealed s- SWCNT FETs exhibited high field-effect mobilities over 5 cm²/Vs in both p-type and n-type operation, along with ideal Vshaped ambipolar transfer curves. These results indicate a significant enhancement in ambipolar performance due to efficient desorption of residual oxygen and water molecules in active channel via high temperature annealing. Furthermore, CMOS-like inverter circuits demonstrated an ideal inversion voltage (VIN = V_DD/2) and a high voltage gain of approximately 9.5. These findings highlight the potential of SWCNT-based materials for realizing next-generation flexible electronic circuits that combine high-performance, energy efficiency, and simplified solution-processing.

Molybdenum disulfide (MoS₂) is a promising 2D semiconductor material for low-power electronics due to its excellent electrical properties and compatibility with conventional processes. In this study, MoS₂ thin films deposited by RF sputtering were etched using Cl₂/Ar plasma in an ICP system. The effects of Cl₂ gas ratio, RF power, and process pressure on etch rate and MoS₂/SiO₂ selectivity were investigated. Optimal results were obtained at 25% Cl₂, achieving ~38 nm/min etch rate and selectivity of 3.0. Increased source power improved both etch rate and selectivity, while higher bias power enhanced etching but reduced selectivity due to stronger ion bombardment. XPS analysis confirmed Mo－Cl and S－Cl bond formation after etching, indicating chemical reactions and some by-product residue. These results provide insights into optimized plasma etching of sputtered MoS₂ films for advanced 2D device fabrication

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

The 4H-SiC VDMOSFET demonstrates a high reverse breakdown voltage (BV) due to the JFET region but experiences relatively high on-resistance (R_on). A widely adopted method to reduce the R_on is to uniformly increase the doping concentration of the JFET region, which results in a trade-off that reduces the BV. This study proposes a method to optimize the segmentation of the JFET region by selectively increasing the doping concentration using ‘total doping’, ‘half-doping’, and ‘quarter-doping’. The optimized quarter segment with a specific doping concentration slightly reduces BV, but the sharp decrease in specific on-resistance (R_on,sp) results in a 105% improvement in the performance index, Baliga’s Figure of Merit (BFOM). This research suggests the potential for electrically superior designs by modifying the doping concentration in the JFET region of conventional VDMOSFET structures.

4H-Silicon carbide (4H-SiC) is a promising material for power and harsh environment devices owing to its superior material properties, including wide bandgap, high critical electric field, and high thermal conductivity. However, despite the advantages of 4H-SiC, its channel mobility is reduced due to the high interface defect density between SiC and the oxide film, leading to increased device switching loss. Therefore, it is necessary to develop new fabrication methods to improve the quality of the SiO₂/4H-SiC interface. According to recent research, the effect of high-temperature (1,250~1,300℃) nitric oxide (NO) annealing on the interface states of SiO₂/4H-SiC and the channel mobility of 4H-SiC metal-oxide-semiconductor-field-effect transistors (MOSFETs) were investigated. Previous studies have optimized the NO post-oxidation annealing (POA) process, using N₂ diluted NO at 1,300℃ to reduce the high SiO₂/4H-SiC interface trap density (D_it). This paper focuses on high-temperature (1,250℃) 10% NO annealing to reduce interface defects by integrating nitrogen atoms into the oxide layer near the SiC interface, potentially increasing the channel mobility. Electrical properties such as D_it, threshold voltage (V_th), field-effect mobility (μ_FE), and specific on-resistance (R_on,sp) were assessed through capacitance-voltage (C-V) and current-voltage (I-V) measurements. It has been confirmed that the interface defect density of the gate oxide film was effectively improved under the POA conditions of 10% NO for 1 hour at 1,250℃.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (Ron,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in Ron,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the Dit.

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

Modern thin film deposition processes require high deposition rates, low costs, and high-quality films. Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) meets these requirements. AP-PECVD causes little damage on thin film deposition surfaces compared to conventional PECVD. Moreover, a higher deposition rate is expected due to the surface heating effect of atomic hydrogens in AP-PECVD. In this study, polycrystalline silicon thin film was deposited at a low temperature of 100℃ and then AP-PECVD experiments were performed with various plasma powers and hydrogen gas flow rates. A deposition rate of 15.2 nm/s was obtained at the VHF power of 400 W. In addition, a metal foam showerhead was employed for uniform gas supply, which provided a significant improvement in the thickness uniformity.

In this research, we evaluated the electrical properties of polycrystalline-gallium-oxide (Ga₂O₃) thin films grown by mist-CVD. A 500~800 nm-thick Ga₂O₃ film was used as a channel in a fabricated bottom-gate MOSFET device. The phase stability of the β-phase Ga₂O₃ layer was enhanced by an annealing treatment. A Ti/Al metal stack served as source and drain electrodes. Maximum drain current (I_D) exceeded 1 mA at a drain voltage (VD) of 20 V. Electron mobility of the β-Ga₂O₃ channel was determined from maximum transconductance (gm), as approximately, 1.39 cm²/Vs. Reasonable device characteristics were demonstrated, from measurement of drain current-gate voltage, for mist-CVD-grown Ga₂O³ thin films.

A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower RDS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys’ process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga’s figure of merit (~94.22 MW/cm²) than the symmetric structure (~46.93 MW/cm²), and the breakdown voltage of the device increases by approximately 70%.

In this study, MOSFETs fabricated on Si-doped, MBE-grown β-Ga₂O₃ are demonstrated. A Si-doped Ga₂O₃ epitaxial layer was grown on a Fe-doped, semi-insulating 1.5 cm × 1 cm Ga₂O₃ substrate using molecular beam epitaxy (MBE). The fabricated devices are circular type MOSFETs with a gate length of 3 μm, a source-drain spacing of 20 μm, and a gate width of 523 μm. The device exhibited a good pinch-off characteristic, a high on-off drain current ratio of approximately 2.7×10⁹, and a high breakdown voltage of 1,080 V, which demonstrates the potential of Ga₂O₃ for power device applications including electric vehicles, railways, and renewable energy.

In this work, we have investigated the effect of a 30-min thermal anneal at 550℃ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.

We propose a method for improving the reliability of a solar cell by applying a fluorinated surface coating to protect the cell from the outdoor environment using an atmospheric pressure plasma (APP) treatment. An APP source is operated by radio frequency (RF) power, Ar gas, and O₂gas. APP treatment can remove organic contaminants from the surface and improve other surface properties such as the surface free energy. We determined the optimal APP parameters to maximize the surface free energy by using the dyne pen test. Then we used the scratch test in order to confirm the correlation between the APP parameters and the surface properties by measuring the surface free energy and adhesive characteristics of the coating. Consequently, an increase in the surface free energy of the cover glass caused an improvement in the adhesion between the coating layer and the cover glass. After treatment, adhesion between the coating and cover glass was improved by 35%.

Herein, we report the manufacture of high-performance, ambipolar organic field-effect transistors (OFETs) and complementary-like electronic circuitry based on a blended, polymeric, semiconducting film. Relatively high and wellbalanced electron and hole mobilities were achieved by incorporating a small amount of ionic additives. The equivalent P-channel and N-channel properties of the ambipolar OFETs enabled the manufacture of complementary-like inverter circuits with a near-ideal switching point, high gain, and good noise margins, via a simple blanket spin-coating process with no additional patterning of each active P-type and N-type semiconductor layer.

Atomically thin MoS₂ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, MoS₂ single-crystal as a transistor channel after transfer onto a SiO2/Si substrate. The MoS2 FETs displayed n-channel characteristics with an electron mobility of 0.05 cm²/V-sec, and a current on/off ratio of ION/IOFF?5×10⁴. Application of bottom-gate voltage stresses, however, increased the interface charges on MoS2/SiO₂, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at 570℃ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above 500℃. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ø_min method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the I_d-V_g relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ø_min method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ø_min method and the TD method reflected the short-channel effect.

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from 10¹³ to 5×10¹⁵ cm^-2 was performed to dope the polycrystalline silicon gate layer. For implant doses of 10¹⁴/㎠ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of 10¹⁴/㎠ or less, which was attributed to the decreased gate current under the gate-depletion effects.

Fe₃O₄ was prepared on the TiO₂-coated natural mica substrate. The natural mica has an average particle size of 22 ㎛. The substrate was coated on TiO₂ thin films using hydrothermal synthesis at pH 1.5-2.5 at 75℃. The Fe precursor solution was prepared by mixing FeSO₄ (for Fe²⁺ ion) and FeCl₃ (for Fe³⁺ ions) with different molar ratios such as 1/2, 1/1, 2/1, 3/0, and Fe₃O₄ only. X-ray diffraction analysis shows that the crystal structure depends on the FeCl₃-to-FeSO₄ molar ratio. Fe₃O₄ crystal phase could be obtained at higher FeSO₄ contents.

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were 8.57 MΩ (Vcc-GND), 14.14 MΩ (Vcc-Input1), 18.24 MΩ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as 2.5 Ω, 50 MΩ, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

MOS-FET structured gas sensors were manufactured using MWCNTs for application as NOx gas sensors. As the gas sensors need to be heated to facilitate desorption of the gas molecules, heat dispersion plays a key role in boosting the degree of uniformity of molecular desorption. We report the desorption of gas molecules from the sensor at 150℃ for different sensor electrode gaps (30, 60, and 90 μm). The COMSOL analysis program was used to verify the process of heat dispersion. For heat analysis, structure of FET gas sensor modeling was proceeded. In addition, a property value of the material was used for two-dimensional modeling. To ascertain the degree of heat dispersion by FEM, the governing equations were presented as partial differential equations. The heat analysis revealed that although a large electrode gap is advantageous for effective gas adsorption, consideration of the heat dispersion gradient indicated that the optimal electrode gap for the sensor is 60 μm.