1전북대학교 신소재공학부 전자재료공학전공
2전북대학교 전자공학부
3전북대학교 나노융합공학과 대학원
MoS₂ has attracted significant attention as a next-generation semiconductor material to overcome the physical scaling limits of silicon-based devices due to its atomic thinness and excellent electrical properties. However, high contact resistance and the formation of Schottky barriers resulting from interface defects during the metal deposition process remain major bottlenecks that degrade overall device performance and reliability. In this study, we fabricated MoS₂ FETs by employing Sb₂Te₃, van der Waals (vdW) contacts. Minimized interface inhomogeneity was achieved through a hemispherical stamp-based dry transfer of h-BN for device encapsulation. h-BN encapsulation decreased the hysteresis window in the ±25 V gate voltage range from 17 V to 11.5 V compared to un-capped devices, confirming that charge trapping phenomena induced by external environmental factors were suppressed. Consequently, the dry transfer technique of h-BN using a hemispherical stamp demonstrated in this study provides a potential solution for securing the long-term reliability of MoS₂ devices with vdW contact by minimizing interface contamination.
