Silicon carbide (SiC) MOSFETs provide superior performance compared to traditional silicon devices under hightemperature and high-power conditions, making them particularly valuable for power electronics applications requiring highfrequency switching and high-energy efficiency. As the electric vehicle (EV) market expands, these devices are commonly packaged into six-pack modules, which can show their different electrical characteristics between the bare-die device and the package due to packaging that improves heat dissipation and other properties. This study uses bare-die SiC MOSFETs to explore their intrinsic characteristics and evaluate their performance in a half-bridge configuration. A half-bridge circuit was constructed, and performance was assessed by varying driving frequencies (10 kHz and 50 kHz) and adjusting the duty cycle between 20% and 80%. Analysis revealed that, at a fixed switching frequency, the average output voltage and average output current are proportional to the duty cycle.

As electric vehicles (EVs) are rapidly adopted worldwide, large numbers are now transported by sea on dedicated car carriers. With this trend, concerns are increasing about fires and explosions caused by battery thermal runaway during marine transport, while existing SOC limits before loading remain largely empirical. This study experimentally investigates gas generation and explosion characteristics of EV lithium-ion cells under thermal runaway conditions representative of enclosed vehicle decks. We identify and quantify the main off-gas components and clarify the flammability behavior and explosion limits of key combustible species. The results provide basic data for assessing EV battery accidents at sea and support the development of safer ventilation and gas-management strategies for ships.

AlGaN/GaN High Electron Mobility Transistors (HEMTs) are emerging as next-generation semiconductors optimized for high-power and high-frequency applications, with their performance highly dependent on the surface and interface quality of the AlGaN/GaN structure. In particular, the 2-Dimensional Electron Gas (2DEG) formed in the AlGaN layer is susceptible to trapping by surface defects, which degrades electrical characteristics and makes the device vulnerable to degradation. In this study, we propose an approach to enhance device reliability and performance by forming a gallium oxynitride (GaON) interfacial layer through O₂ plasma treatment on the AlGaN surface. This method effectively suppresses interface defects, resulting in improved electrical properties such as reduced interface trap density (Dit), threshold voltage (Vth) shift, increased drain current density (Id), and enhanced transconductance density (gm). Furthermore, this surface treatment demonstrates the potential for process simplification by improving the electrical characteristics of power semiconductor devices without the need for complex deposition steps.

Silicon carbide (SiC) power devices are attracting increasing attention for high-voltage and high-efficiency applications due to their superior material properties. However, achieving an optimal trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV) remains a key design challenge in planar MOSFET structures. In this study, twodimensional TCAD simulations were conducted to investigate the impact of varying the doping concentrations of the P-well (from 3 × 10¹⁷ to 6 × 10¹⁷ cm^-3) and JFET regions (from 1 × 10¹⁶ to 7 × 1016 cm^-3) on the electrical characteristics of 2.4 kVclass planar SiC MOSFETs. To maintain comparable BV conditions for 2.4 kV operation, two groups with P-well doping concentrations of 4.5 × 10¹⁷ cm^-3 and 5.3 × 1017 cm^-3 were analyzed and compared. When the P-well and JFET doping concentrations were 4.5 × 10¹⁷ cm^-3 and 1.5 × 10¹⁶ cm^-3, respectively, the simulated Ron,sp and BV were 1.41 mΩ·cm² and 3,150 V. In contrast, with P-well and JFET doping concentrations of 5.3 × 10¹⁷ cm^-3 and 5.0 × 10¹⁶ cm^-3, the Ron,sp was reduced to 1.31 mΩ·cm² while the BV slightly increased to 3,200 V. Based on these results, an optimized device structure was proposed, demonstrating its potential for integration into high-voltage SiC-based power systems. This study provides practical design insights and is expected to contribute to the advancement of wide bandgap semiconductor technologies for next-generation power electronics.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

In this study, we proposed β-Ga₂O₃ JFET using nitrogen doping and analyzed the electrical characteristics. In β-Ga₂O₃, nitrogen ions act as a deep acceptor and are used to implement the current blocking layer. By using this characteristic of the nitrogen ion, in the proposed JFET, nitrogen ions are used to obtain gate control and pinch off the channel of the JFET. The numerical TCAD simulation was performed to design and analyze the proposed JFET. The simulated forward and reverse characteristics of the proposed JFET were obtained as a function of JFET width and nitrogen doping concentration. The maximum breakdown voltage of 1.7 kV was obtained with the on-resistance of 16.7 mΩ·cm² when the channel width was 1.5 μm and nitrogen doping concentration is 1×1018/cm³, respectively.

This paper presents a Si-NWFET-based LC-VCO design that includes an SCA, a P-type Si-NWFET varactor, a 1.2 nH LC tank, and a bias network to linearize the varactor’s C-V characteristics, enabling a wide oscillation frequency tuning range. The circuit achieves a 24 GHz oscillation frequency with a low power consumption of 16.8 μW at a control voltage (V_ctrl) of 0.7 V. Phase noise simulations indicate an excellent -109.62 dBc/Hz at a 1 MHz offset, confirming its applicability for RFIC systems. Additionally, the proposed LC-VCO demonstrates stable performance in five major corner process analyses, ensuring robustness under extreme conditions. These results validate the durability of the design and highlight the potential of Si-NWFETbased LC-VCOs as a viable, low-power, highly integrated solution for RFIC applications. The findings underscore the suitability of Si-NWFET technology as a promising alternative to current FinFET and CMOS processes in advanced circuit design.

The 4H-SiC VDMOSFET demonstrates a high reverse breakdown voltage (BV) due to the JFET region but experiences relatively high on-resistance (R_on). A widely adopted method to reduce the R_on is to uniformly increase the doping concentration of the JFET region, which results in a trade-off that reduces the BV. This study proposes a method to optimize the segmentation of the JFET region by selectively increasing the doping concentration using ‘total doping’, ‘half-doping’, and ‘quarter-doping’. The optimized quarter segment with a specific doping concentration slightly reduces BV, but the sharp decrease in specific on-resistance (R_on,sp) results in a 105% improvement in the performance index, Baliga’s Figure of Merit (BFOM). This research suggests the potential for electrically superior designs by modifying the doping concentration in the JFET region of conventional VDMOSFET structures.

4H-Silicon carbide (4H-SiC) is a promising material for power and harsh environment devices owing to its superior material properties, including wide bandgap, high critical electric field, and high thermal conductivity. However, despite the advantages of 4H-SiC, its channel mobility is reduced due to the high interface defect density between SiC and the oxide film, leading to increased device switching loss. Therefore, it is necessary to develop new fabrication methods to improve the quality of the SiO₂/4H-SiC interface. According to recent research, the effect of high-temperature (1,250~1,300℃) nitric oxide (NO) annealing on the interface states of SiO₂/4H-SiC and the channel mobility of 4H-SiC metal-oxide-semiconductor-field-effect transistors (MOSFETs) were investigated. Previous studies have optimized the NO post-oxidation annealing (POA) process, using N₂ diluted NO at 1,300℃ to reduce the high SiO₂/4H-SiC interface trap density (D_it). This paper focuses on high-temperature (1,250℃) 10% NO annealing to reduce interface defects by integrating nitrogen atoms into the oxide layer near the SiC interface, potentially increasing the channel mobility. Electrical properties such as D_it, threshold voltage (V_th), field-effect mobility (μ_FE), and specific on-resistance (R_on,sp) were assessed through capacitance-voltage (C-V) and current-voltage (I-V) measurements. It has been confirmed that the interface defect density of the gate oxide film was effectively improved under the POA conditions of 10% NO for 1 hour at 1,250℃.

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (Ron,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in Ron,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

Citations

• A Review on Energy Yield Enhancement Characteristics of Bifacial Photovoltaic Systems Combined with Solar Tracking
  Hyeong Gi Park
  Journal of Electrical and Electronic Materials.2026; 39(4): 309.     CrossRef

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the Dit.

Recently, as interest in personal hygiene has increased due to the community spread of COVID-19 and variant viruses, fixed and potable UV germicidal equipment to sterilize indoor spaces and hand-held UV germicidal equipment to sterilize household items such as masks and mobile phones are continuously being developed and sold. However, the development and sales of the product are difficult because appropriate testing methods have not yet been established. In this situation, if an uncertified product is distributed in the market, it can cause serious harm to consumers. In this study, we investigate the photobiological risks and safety devices against UV exposure of UV germicidal equipment distributed domestically, and propose appropriate test methods for portable UV germicidal equipment based on the research results.

This paper presents the development and market trends of nano biosensors. These biosensors must possess high sensitivity and selectivity to effectively detect diseases. Presently, many research groups are focusing on the field-effect transistor aspect of nano biosensors, which can identify diseases such as Down syndrome, bladder cancer, breast cancer, and numerous other cancers, utilizing graphene and transition metal dichalcogenide materials. In the case of in-vitro diagnostics, the use of nano biosensors has been rapidly growing since the onset of the COVID-19 pandemic. This paper also discusses market trends and the outlook for both national and international enterprises engaged in the nano biosensor field. Nano biosensors are expected to play a beneficial and significant role soon, contributing to the early diagnosis of diseases and subsequently improving patient outcomes.

With the purpose of instilling an awareness of the safety of users of electrical equipment and inducing voluntary facility improvement through the safety rating system for general low voltage electrical equipment, simulation and field application of the safety rating of general low voltage electrical equipment were conducted. For the introduction and application of the safety rating system for general low-voltage electrical equipment, data related to domestic safety was investigated and analyzed, cases of introduction in other fields were reviewed, and for design, the 4M risk assessment method of the Korea Occupational Safety and Health Agency and the cases of safety index development in Korea were analyzed and standardized. Safety rating system simulations were conducted for general low-voltage electrical equipment, and problem improvement measures were prepared by analyzing the results through on-site verification and simulation applied to the initial design. Design standards for the introduction of the safety rating system for general low-voltage electrical equipment were prepared, and 394 youth training facilities were applied to the field to see if the design standards were practically applicable to the field. With the application of the safety rating system for low-voltage electrical equipment for general use, youth training facilities that had been classified as ‘appropriate’ were able to induce an upgrade to a higher level through voluntary facility improvement according to the application of grades (A to E). As a result of inducing voluntary repair projects based on the results of the 1st and 2nd inspection of youth training facilities, it was confirmed that 86 facilities received grade A, 225 facilities received grade B, and only 311 facilities received grade A to B out of a total of 394 facilities, and there was no grade E.

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1 × 10¹⁷ to 1 × 10¹⁹ cm^-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1 × 10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1 × 10^-3 A/mm.

Recently, sterilization technology has received increasing interest due to the COVID-19 pandemic and required safety precautions. Particularly, sterilization devices using near ultraviolet (UV) with a 405 nm wavelength are also drawing attention. It has a UV-C wavelength and other sterilization effects. Its blue-colored light on the boundary between UV and visible light is used as a light-emitting diode (LED) lamp for 405 nm sterilization, owing to its longer wavelengths than UV rays. However, the 405 nm wavelength contains blue light that can damage the eyes and skin during prolonged exposures and affect the emotional and biological parts of the body. Currently, 405 nm sterilization LED light registers are circulating in the market. However, they have not undergone safety tests for blue-light hazards. Thus, with the active distribution of sterilization LED lights, solid safety standards and management systems are essential to protect users from blue-light hazards. Accordingly, in this study, we conducted spectral radiance and spectral radiative luminance tests on 405 nm sterilization LED registers available in the market by the measurement criteria of IEC 62471. Safety standards must be established to secure users' safety against blue light hazards at a time when 405nm sterilization LED lights are actively distributed due to COVID-19.

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

Despite otherwise advantageous properties, the performance and reliability of devices manufactured in ß-Ga₂O₃ on semi-insulating Ga₂O₃ substrates may degrade because of poorly mitigated self-heating, which results from the low thermal conductivity of Ga₂O₃ substrates. In this work, we investigate and compare self-heating and device performance of β-Ga₂O₃ MESFETs on substrates of semi-insulating Ga₂O₃ and 4H-SiC. Electron mobility in β-Ga₂O₃ is negatively affected by increasing lattice temperature, which consequently also negatively influences device conductance. The superior thermal conductivity of 4H-SiC substrates resulted in reduced ß-Ga₂O₃ lattice temperatures and, thus, mitigates MESFET drain current degradation. This, in turn, allows practically reduced device dimensions without deteriorating the performance and improved device reliability.

Field-effect transistors (FETs) are the key elements of conventional electronics; hence, have drawn a lot of research and commercial interests. In recent years, metal halide perovskite materials have achieved a remarkable efficiency of 29.15% in the field of photovoltaics, and have drawn the scientific community’s attention to promote their use in the field of optoelectronics, such as FETs and phototransistors. The MAPbI₃ (methylammonium lead iodide) perovskite TFT has achieved a record hole mobility of 21.41 ㎠/V-s in the year 2020. In this review, we will briefly discuss the physical structure of MAPbI₃ perovskite and the essential factors that stimulate these devices, together with the role of defects, the ion migration concept, and the implication of both dielectric and electrode materials on the device’s performance.

The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

In this research, we evaluated the electrical properties of polycrystalline-gallium-oxide (Ga₂O₃) thin films grown by mist-CVD. A 500~800 nm-thick Ga₂O₃ film was used as a channel in a fabricated bottom-gate MOSFET device. The phase stability of the β-phase Ga₂O₃ layer was enhanced by an annealing treatment. A Ti/Al metal stack served as source and drain electrodes. Maximum drain current (I_D) exceeded 1 mA at a drain voltage (VD) of 20 V. Electron mobility of the β-Ga₂O₃ channel was determined from maximum transconductance (gm), as approximately, 1.39 cm²/Vs. Reasonable device characteristics were demonstrated, from measurement of drain current-gate voltage, for mist-CVD-grown Ga₂O³ thin films.

This study tested the electrical, structural, and thermal safety of LED lighting products, available on the market. Five recessed LED systems, 20 W each, and five fixed LED systems, 25 W each, were selected. Dielectric strength tests, live part electric shock protection tests, and thermal tests were conducted on the LEDs. These were key tests for user safety, according to the specification of the safety criteria for electric products, KC 60598-1, South Korea. In addition, the wiring temperature of UL1007, 60227 IEC 08, and UTP cables, was measured. The results of the study gave an in-depth examination of the safety of LED lighting systems for users.