Micro-LEDs show lower efficiencies compared to general LEDs having large areas. Simulations were carried out using ray-tracing software to investigate the change in light extraction efficiency and light distribution according to chip-size of blue flip-chip micro-LEDs (FC μ-LEDs). After fixing the height of the square FC μ-LED chip at 158 μm, the length of one side was varied, with dimensions of 2, 5, 10, 30, 50, 100, 300, and 500 μm. The highest light-extraction efficiency was obtained at 10 μm, beyond which the efficiency decreased as the chip-size increased. The chip size-dependence of the FC μ-LEDs both without the patterned sapphire substrate, as well as vertical FC μ-LEDs, were analyzed.

The improvement of irradiation intensity and irradiation uniformity is essential for large area and high power UVA light source application. In this study, large number of chips bonded by micro soldering technique were driven by low current, and current limiting diodes were configured to supply constant current to parallel circuits consisting of large number of series strings. The dimension of light source module circuit board was 350 × 90 mm2 and 16,650 numbers of 385 nm flip chip LEDs were used with a configuration of 90 parallel and 185 series strings. The space between LEDs in parallel and series strings were maintained at 1.9 mm and 1.0 mm distance, respectively. The size of the flip chip was 750 × 750 μm2 were used with contact pads of 260 × 669 μm2 size, and SAC (96.5 Sn/3.0 Ag/0.5 Cu) solder was used for flip chip bonding. The fabricated light source module with 7.5 m A supply current showed temperature rise of 66℃, whereas irradiation was measured to be 300 mW/cm2. Inaddition, 0.23% variation of the constant current in each series string was demonstrated.

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

The alumina substrates that Ni electrode was printed on and the multi-layered PTCR thermistors of which composition is (Ba_0.998Ce_0.002)TiO_3 + 0.001MnCO_3 + 0.05BN were fabricated by a thick film process, and the effect of re-oxidation temperature on their resistivities and resistance jumps were investigated, respectively. Ni electroded alumina substrate and the multi-layered PTC thermistor were sintered at l,150℃ for 2 h under PO_2= 10^-6 Pa and then re-oxidized at 600∼850℃ for 20 min. With increasing the re-oxidation temperature, the room temperature resistivity increased and the resistance jump (LogR_290/R_25) decreased, which seems to be related to the oxidation of Ni electrode. The small sized chip PTC thermistor such as 2012 and 3216 exhibits a nonlinear and rectifying behavior in I-V curve but the large sized chip PTC thermistor such as 4532 and 6532 shows a linear and ohmic behavior. Also, the small sized chip PTC thermistor such as 2012 and 3216 is more dependent on the re-oxidation temperature and easy to. be oxidized in comparison with the large sized chip PTC thermistor such as 4532 and 6532. So, the re-oxidation conditions of chip PTC thermistor may be determined by considering the chip size.

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um × 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

Modified structure of copper pillar bump which has trapezoidal cross section on the top region is suggested with simulation results and concept of fabrication process. Due to the large surface area of joint region between bump and solder in suggested structure, electro-migration effect can be reduced. Reduction of electro-migration is related with current density and joule heating in bump and investigated with finite element methods with variation of dimensional parameters. Mechanical characteristics are also investigated with comparing modified copper pillar bump and conventional copper pillar bump.

The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850∼900℃ for 1 h in air. A good varistor characteristics (Vn= 9.3∼15.4 V, a= 23∼24, IL= 1.0∼1.6 μA) were revealed but formed Zn(i)·· (0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.