In this paper, matching characteristic of MIM (metal-insulator-metal) capacitor with Al2O3/HfO2/Al2O3 (AHA) structure is analyzed. The floating gate capacitance measurement technique (FGMT) was used for analysis of matching characteristic of the MIM capacitors in depth. It was shown that matching coefficient of AHA MIM capacitor is 0.331%㎛ which is appropriate for application to analog/RF integrated circuits. It was also shown that the matching coefficient has a more strong dependence on the width than length of MIM capacitor.

For integrated complementary metal oxide semiconductor (CMOS) circuits, the lateral spread for two-dimensional (2-D) impurity distributions are very important for the analyzing the devices. The measured two-dimensional SEM data obtained using the chemical etching-method matched very well with the results of the Gauss model for boron implanted samples. But the profiles in boron implanted silicon were deviated from the Gauss model. The profiles in boron implanted silicon were shown a little bit steep profile in the deep region due to backscattering effect on the near surface from the bombardments of light boron ions. From the simulated 3-D data obtained using an analytical model, the 1-D and 2-D data were compared with the experimental data and could be verified the justification from the experimental data. The data of 3-D model were also shown good agreements with the experimental and the simulated data. It can be used in the 3-D chip design and the analysis of microelectro-mecanical system (MEMS) and special devices.

Presented herein are the results of the study that was conducted on the electrical characteristics of organic field-effect transistors based on poly(3-hexylthiophene), particularly the thickness and annealing temperature of their active layer is varied. The changes in field-effect mobility and current on/off ratio were explored. It was observed that both increasing annealing temperature from 60℃ to 100℃ and various concentrations influence the trade-off relations between the mobility and current on/off ratio. The surface morphology of the 2-μm2 area with various thicknesses was scanned via atomic-forcemicroscopy(AFM) to verify the relationship between surface morphology, which is related to the thickness of the film, and device performance.

In this paper, we investigated the device performance on fluorine implantation, hot carrier reliability and RTS (random telegraph signal) noise characteristics of NMOSFETs. The capacitance of the fluorine implanted NMOSFET decreased due to the increase of the gate oxide thickness. RTS noise characteristics of the fluorine implated NMOSFET was improved approximately by 46% due to the decrease of trap density at Si/SiO2 interface. The improved gate oxide quality also results in the longer hot carrier life time.

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO Ψ -MOSFET) with a stacked Si3N4/SiO2 (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a SiO2 buffer layer. The roles of a SiO2 buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and Si3N4. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick SiO2 buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin SiO2 buffer layer which highlighted bias and light-induced hole trapping into the Si3N4 layer. As a results, the pseudo-MOS transistor with a 20-nm-thick SiO2 buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(μFE) of 12.3 cm2/V·s, subthreshold slope (SS) of 148 mV/dec, trap density (Nt) of 4.52× 1011 cm-2, negative bias illumination stress (NBIS) ΔVth of 1.23 V, and negative bias temperature illumination stress (NBTIS) ΔVth of 2.06 V.

Lead-free 0.98(Na0.5,K0.5)NbO3-0.02Li(Sb0.17Ti0.83)O3 (hereafter 0.98NKN-0.02LST) ceramics doped with Ag2O were prepared using a conventional mixed oxide method. The specimen showed superior structural and electrical properties when 1 mol% Ag2O was doped. For the 0.98NKN-0.02LST+1.0 mol%Ag2O ceramics sintered at 1,100℃, piezoelectric constant (d33) of sample showed the optimum values of 207 pC/N. The 0.98NKN-0.02LST+1.0 mol%Ag2O ceramics are a promising candidate for lead-free piezoelectric materials.

In this study, the thickness effects of Al2O3 layer on the sensing properties of SiO2/Al2O3 (OA) stacked membrane were investigated using electrolyte-insulator-semiconductor (EIS) structure for high quality pH sensor. The Al2O3 layers with a respective thickness of 5 nm, 15 nm, 23 nm, 50 nm, and 100 nm were deposited on the 5-nm-thick SiO2 layers. The electrical characteristics and sensing properties of each OA membranes were investigated using metal-insulator-semiconductor (MIS) and EIS devices, respectively. As a result, the OA stacked membrane with 23-nm-thick Al2O3 layer shows the excellent characteristics as a sensing membrane of EIS sensor, which can enhance the signal to noise ratio.

We were studied that AZO conductive thin film can substitute for FTO electrode in dye sensitized solar cell. Three types of AZO films were deposited on soda-lime glass(AZO/glass, AZO/AZO/glass, textured AZO/AZO/glass) using RF magnetron sputtering process and investigated their properties of electrical, optical, and photoelectric conversion rate. The textured AZO/AZO/glass has the lowest resistivity of 3.079×10-4 Ω㎝ among other films. And the optical transmittance rate was better than both non textured AZO/AZO/glass and FTO/glass in the visible region. After manufacturing dye solar cells using the three types of AZO films, the textured AZO/AZO/glass showed the highest photoelectric conversion rate of 3.68% among AZO samples. But the transformation rate was slightly lower than FTO cells (4.52%). However, the conductive film of textured AZO/AZO/glass can be applicable to use an electrode in solar cells as cost-effective products.

The TiO2/Si3N4/Ag/Si3N4/TiO2 multi layered structure was designed for the possible application of transparent electrodes in PDP (Plasma Display Panel). Multi layered film was deposited on a glass substrate at room temperature by DC/RF magnetron sputtering system and EMP (Essential Macleod Program) was adopted to optimize the optical characteristics of film. During the deposition process, the Ag layer in TiO2/Ag/TiO2 became heavily oxidized and the filter characteristic was degraded easily. In thus study, Si3N4 layer was used as a diffusion buffer layer between TiO2 and Ag. in order to prevent the oxidation of Ag layer in TiO2/Si3N4/Ag/Si3N4/TiO2 structure. It was confirmed that Si3N4 layer is one of candidate materials acting as diffusin barrier between TiO2/Ag/TiO2.

The charged particle type display device is a kind of the reflectivity type display and shows an image by absorption and reflection of external light source. The charged particle is important factor for driving of the display and quantity of charge per mass of the charged particle determines the driving voltage, contrast ratio, response time, etc. But it is easy for the charged particles to be damaged in the putting process of the display and the damages cause lumping phenomenon of the charged particles. Because the lumping phenomenon makes high driving voltage, low quality of optical properties, short life time, etc, so the charged particles must be filled by stable putting methods. In this paper, we filled the charged particles into the panels by electric fields to improve the electrical and optical characteristics of the display. Also, we analyzed the driving characteristics of the charged particles according to the applied putting voltages.

In this paper, by designing 20 W class driving circuit for driving high-power LED (Light Emitting Diode), we are going to comparatively carry out the analysis of characteristics for power circuit according to each design method. In this case, 200 V 60 Hz was performed as input data. The electrical characteristics such as voltage, current and ripple are checked for constant current circuit and constant voltage circuit in the LED module. In addition, as the ripple has an influence on illumination of LED light, low temperature working (-20 [℃]) and high temperature working(80 [℃]) are measured to make sure the ripple characteristics in accordance with temperature. In low temperature operation -20 [℃] measurements, both constant current circuit and constant-voltage circuit were less impacted on input fluctuation, whereas in the high temperature operation 80 [℃], current voltage in constant voltage circuit was surge after 430 [hour]. Voltage current ripple of constant current circuit was much less than constant voltage circuit, therefore we can show that constant current circuit is more stable.

In our report a relatively simple process for fast nano-texturing of p-type(100) CZ- silicon surface using silver catalyzed wet chemical etching in aqueous hydrofluoric acid (HF) and hydrogen peroxide solution(H2O2) at room temperature. The wafers were saw-damaged by NaOH(6 wt%) at 60℃ for 150s. To obtain a nano-structured black surface, a thin layer of silver with thickness of 1 - 10 nm was deposited on the surfaces by evaporation system. After this process the samples were etched in HF : H2O2 : H2O = 1:5:10 at room temperature for 80s - 220s. Due to the local catalytic of the Ag clusters, this treatment results in the nano-scale texturing on the surface. This resulted in average reflectance values less than 9% after the silver on the surface of the wafers were removed.

Owing to the rapid growth of mobile and electronic equipment miniaturization technology, the supply of micro mobile computing machine has been fast raised. Accordingly they have performed many researches on energy harvesting technology to provide promising power supply equipment to substitute existing batteries. In this paper, in order to have low resonance frequency for piezoelectric energy harvester, we have tried to make it larger than before by adopting nickel that has much higher density than silicon. We have applied it for our energy harvesting actuator instead of the existing silicon based actuator. Through such new concept and approach, we have designed energy harvesting device and made it personally by making with micromachining process. The energy harvester structure has a cantilever type and has a dimension of 10×2.5×0.1 mm3 for length, width and thickness respectively. Its electrode type is formed by using Au/Ti of interdigitate d33 mode. The pattern size and gap size is 50 μm. Based on the measurement of the nickel-based piezoelectric energy harvester, it is found to have 778 Hz for a resonant frequency with no proof mass. In that resonance frequency we could get a maximum output power of 76 μW at 4.8 MΩ being applied with 1 g acceleration.

This paper presents a comparative analysis of the parallel operation of different switches in a DC/DC converter. In high power applications, multi-switch PWM power conditioners may be preferred despite a higher component count, due to the absence of low frequency filters, reduced switching losses and fault tolerance. The paper demonstrates how current sharing (CSH) and time sharing (TSH) lead to the reduction of switching stress in the parallel operation of switches in any converter. The solutions proposed in this study can be applied on different scales to other power conditioners for DC/DC converter systems. Discussions of the concepts, hypotheses and computer simulations are verified by 1 kW experimental results.

In a real-time indoor place recognition system using image features detection, specific markers included in input image should be detected exactly and quickly. However because the same markers in image are shown up differently depending to movement, direction and angle of camera, it is required a method to solve such problems. This paper proposes a technique to extract the features of object without regard to change of the object scale. To support real-time operation, it adopts SURF(Speeded up Robust Features) which enables fast feature detection. Another feature of this system is the user mark designation which makes possible for user to designate marks from input image for location detection in advance. Unlike to use hardware marks, the feature above has an advantage that the designated marks can be used without any manipulation to recognize location in input image.