In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO Ψ -MOSFET) with a stacked Si3N4/SiO2 (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a SiO2 buffer layer. The roles of a SiO2 buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and Si3N4. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick SiO2 buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin SiO2 buffer layer which highlighted bias and light-induced hole trapping into the Si3N4 layer. As a results, the pseudo-MOS transistor with a 20-nm-thick SiO2 buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(μFE) of 12.3 cm2/V·s, subthreshold slope (SS) of 148 mV/dec, trap density (Nt) of 4.52× 1011 cm-2, negative bias illumination stress (NBIS) ΔVth of 1.23 V, and negative bias temperature illumination stress (NBTIS) ΔVth of 2.06 V.
