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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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LED Driver ICs칩의 소형화를 위한 Chip on Chip 기술에 관한 연구

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Regular Paper : Study on Chip on Chip Technology for Minimizing LED Driver Ics

Ey Goo Kang
J Electr Electron Mater 2016;29(3):131-134.
Published online: March 1, 2016
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This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

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Regular Paper : Study on Chip on Chip Technology for Minimizing LED Driver Ics
J Electr Electron Mater. 2016;29(3):131-134.   Published online March 1, 2016
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Regular Paper : Study on Chip on Chip Technology for Minimizing LED Driver Ics
J Electr Electron Mater. 2016;29(3):131-134.   Published online March 1, 2016
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