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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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비트 SONOS 전하트랩 플래시메모리를 구현하기 위한 기판 바이어스를 이용한 2단계 펄스 프로그래밍에 관한 연구

김병철, 강창수, 이현용, 김주연

A Study on a Substrate-bias Assisted 2-step Pulse Programming for Realizing 4-bit SONOS Charge Trapping Flash Memory

Byung Cheul Kim, Chang Soo Kang, Hyun Yong Lee, Joo Yeon Kim
J Electr Electron Mater 2012;25(6):409-413.
Published online: June 1, 2012
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In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

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A Study on a Substrate-bias Assisted 2-step Pulse Programming for Realizing 4-bit SONOS Charge Trapping Flash Memory
J Electr Electron Mater. 2012;25(6):409-413.   Published online June 1, 2012
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
A Study on a Substrate-bias Assisted 2-step Pulse Programming for Realizing 4-bit SONOS Charge Trapping Flash Memory
J Electr Electron Mater. 2012;25(6):409-413.   Published online June 1, 2012
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