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0.25 ㎛ 표준 CMOS 로직 공정을 이용한 Single Polysilicon EEPROM 셀 및 고전압소자

신윤수, 나기열, 김영식, 김영석

Single Polysilicon EEPROM Cell and High-voltage Devices using a 0.25 ㎛ Standard CMOS Logic Process

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J Electr Electron Mater 2006;19(11):994-999.
Published online: November 1, 2006
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Single Polysilicon EEPROM Cell and High-voltage Devices using a 0.25 ㎛ Standard CMOS Logic Process
J Electr Electron Mater. 2006;19(11):994-999.   Published online November 1, 2006
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
Single Polysilicon EEPROM Cell and High-voltage Devices using a 0.25 ㎛ Standard CMOS Logic Process
J Electr Electron Mater. 2006;19(11):994-999.   Published online November 1, 2006
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