The rapid advancement of large-scale language models and artificial intelligence technologies has highlighted the importance of data processing efficiency. This study outlines a measurement optimization method for high-speed pulse equipment to accurately analyze the operating dynamics of ReRAM, a core hardware component for simulating neural networks. An optimized evaluation methodology combining connection compensation and a dual-channel configuration was established to minimize measurement errors caused by parasitic resistance and capacitance during pulse measurements using the Keithley 4200A-SCS and 4225-PMU modules, and to address HRS/LRS measurement errors caused by mismatches between the measurement range and source limits. The proposed precision measurement guidelines can be applied to the evaluation of semiconductor devices that require pulse measurements, such as transistors and DRAM.

MoS₂ has attracted significant attention as a next-generation semiconductor material to overcome the physical scaling limits of silicon-based devices due to its atomic thinness and excellent electrical properties. However, high contact resistance and the formation of Schottky barriers resulting from interface defects during the metal deposition process remain major bottlenecks that degrade overall device performance and reliability. In this study, we fabricated MoS₂ FETs by employing Sb₂Te₃, van der Waals (vdW) contacts. Minimized interface inhomogeneity was achieved through a hemispherical stamp-based dry transfer of h-BN for device encapsulation. h-BN encapsulation decreased the hysteresis window in the ±25 V gate voltage range from 17 V to 11.5 V compared to un-capped devices, confirming that charge trapping phenomena induced by external environmental factors were suppressed. Consequently, the dry transfer technique of h-BN using a hemispherical stamp demonstrated in this study provides a potential solution for securing the long-term reliability of MoS₂ devices with vdW contact by minimizing interface contamination.

The solution-based fabrication process for resistive random-access memory (ReRAM) offers several advantages over conventional vapor deposition processes, including simplicity, cost-effectiveness, and high versatility for coating complex structures over large areas. In this study, a TiO₂-based ReRAM device was fabricated using a solution process with Pt top and P⁺⁺-Si bottom electrodes. The synthesized TiO₂ films contain a residual Cl element as revealed by X-ray photoelectron spectroscopy (XPS). Reversible volatile resistance switching was observed due to the formation of conductive Ti-O-Ti networks in the TiO₂ layer. Post-annealing led to an increase in the threshold voltage (Vth). Asymmetric Current-Voltage characteristics was observed due to the different in the work functions of the electrodes. Additionally, the influence of compliance current settings on filament formation and hysteresis behavior was systematically investigated. The results demonstrated that higher compliance currents enhanced the hysteresis width for both positive and negative voltage bias conditions.

Citations

• Pulse Response Measurement Optimization of ReRAM-Based Neuromorphic Devices
  Soon Joo Yoon, Yoon Kyeung Lee
  Journal of Electrical and Electronic Materials.2026; 39(3): 258.     CrossRef

In this study, the electrical properties of zinc oxide (ZnO) thin-film transistors (TFTs) based on oxide semiconductors were analyzed. As interest in next-generation transparent and flexible displays grows, ZnO, which offers high field-effect mobility and transparency, has emerged as a promising material to overcome the limitations of amorphous silicon (a-Si)-based TFTs. ZnO has a wide bandgap and optical transparency and can be deposited on various substrates at low temperatures, making it a suitable channel material for future display devices. In this study, ZnO TFTs were fabricated with an inverted staggered structure using a p⁺⁺ Si wafer coated with SiO₂ as the substrate. The ZnO channel layer was deposited by RF magnetron sputtering, and the ITO source/drain electrodes were formed using an e-beam evaporator. The electrical characteristics was evaluated using Keithley 4200A-SCS parameter analyzer. Mobility, On/Off ratio, and subthreshold swing (SS) were calculated from the measurements.

The report reviews recent research efforts in demonstrating a computing system whose operation principle mimics the dynamics of biological neurons. The temporal variation of the membrane potential of neurons is one of the key features that contribute to the information processing in the brain. We first summarize the neuron models that explain the experimentally observed change in the membrane potential. The function of ion channels is briefly introduced to understand such change from the molecular viewpoint. Dedicated circuits that can simulate the neuronal dynamics have been developed to reproduce the charging and discharging dynamics of neurons depending on the input ionic current from presynaptic neurons. Key elements include volatile memristors that can undergo volatile resistance switching depending on the voltage bias. This behavior called the threshold switching has been utilized to reproduce the spikes observed in the biological neurons. Various types of threshold switch have been applied in a different configuration in the hardware demonstration of neurons. Recent studies revealed that the memristor-based circuits could provide energy and space efficient options for the demonstration of neurons using the innate physical properties of materials compared to the options demonstrated with the conventional complementary metal-oxidesemiconductors (CMOS).