Long lifetime, low power consumption, and environmental friendliness have enabled light-emitting diode (LED) lighting to rapidly replace conventional light sources such as incandescent and fluorescent lamps. In particular, AC-LED lighting systems can be directly powered by commercial alternating current (AC) sources; however, they suffer from significant luminance deviation caused by uneven current distribution among LED light-emitting modules. This paper proposes a lighting control method that improves flicker performance while maintaining lamp brightness and effectively reduces luminance deviation in AC-LED lighting. The proposed method reduces luminance deviation by controlling the lighting order of multiple LED light-emitting modules. Among four LED modules, only the required number of modules is continuously turned on, and the lighting priority alternates between rectification cycles. Specifically, during odd rectification cycles, LED modules are activated sequentially in ascending order (11→12→13→14), whereas during even rectification cycles, they are activated in descending order (14→13→12→11). By alternately applying continuous lighting control with opposite activation orders, the proposed reverse alternating lighting control method equalizes the current distribution among LED modules. As a result, luminance uniformity is improved, electrical stress concentration on specific modules is reduced, and the operational lifetime of the LED modules is extended compared with the conventional fixed-sequence lighting control method.
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Reduction of Luminance Deviation in Multi-Module AC-LED Lighting Systems Using a Circular Sequential Lighting Control Method Dong Won Lee, Byungcheul Kim Journal of Electrical and Electronic Materials.2026; 39(3): 267. CrossRef
In order to spread LED lighting, LED lighting technology directly driven by alternating current (AC) commercial power has recently been introduced. Since current does not flow at a voltage lower than the threshold voltage of the LED, a nonconductive section occurs in the current waveform, and the higher the threshold voltage of the LED, the more discontinuous current waveforms are generated. In this paper, multi-LED modules are connected in series so that the threshold voltage can be adjusted according to the number of LED modules. A small number of LED modules are driven at a low instantaneous rectified voltage, and a large number of LED modules are driven at a high instantaneous rectified voltage to lengthen the overall lighting time of AC-LED lighting, thereby minimizing the luminance deviation of AC-LED lighting. In addition, the load current flowing through the LED module is adjusted to be the same as the design current even at the maximum rectified voltage higher than the design voltage, so that the light brightness of the LED module is kept constant. Therefore, even if the rectified voltage applied to the LED module changes, the AC-LED lighting in which the light brightness is constant and the luminance deviation is minimal has been realized.
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Reduction of Luminance Deviation in Multi-Module AC-LED Lighting Systems Using a Circular Sequential Lighting Control Method Dong Won Lee, Byungcheul Kim Journal of Electrical and Electronic Materials.2026; 39(3): 267. CrossRef
This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.
The subthreshold swing (SS) of an asymmetric junctionless double gate (AJLDG) MOSFET is analyzed by the use of Gaussian function. In the asymmetric structure, the thickness of the top/bottom oxide film and the flat-band voltages of top gate (Vfbf) and bottom gate (Vfbb) could be made differently, so the change in the SS for these factors is analyzed with the projected range and standard projected deviation which are parameters for the Gaussian function. An analytical subthreshold swing model is presented from the Poisson’s equation, and it is shown that this model is in a good agreement with the numerical model. As a result, the SS changes linearly according to the geometric mean of the top and bottom oxide film thicknesses, and if the projected range is less than half of the silicon thickness, the SS decreases as the top gate oxide film is smaller. Conversely, if the projected range is bigger than a half of the silicon thickness, the SS decreases as the bottom gate oxide film is smaller. In addition, the SS decreases as Vfbb-Vfbf increases when the projected range is near the top gate, and the SS decreases as Vfbb-Vfbf decreases when the projected range is near the bottom gate. It is necessary that one should pay attention to the selection of the top/bottom oxide thickness and the gate metal in order to reduce the SS when designing an AJLDG MOSFET.
With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.
In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 [mm2]. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.
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Reflection Characteristics of Electroplated Deposits on LED Lead frame with Plating Condition SeHo Kee, Wonjoong Kim, JaePil Jung Journal of the Microelectronics and Packaging Society.2013; 20(2): 29. CrossRef
Anisotropic Wet-Etching Process of Si Substrate for Formation of Thermal Vias in High-Power LED Packages B.K. Yu, M.Y. Kim, T.S. Oh Journal of the Microelectronics and Packaging Society.2012; 19(4): 51. CrossRef
Solder Bump Deposition Using a Laser Beam Won-Suk Choi, Jea-Woon Kim, Jong-Hyeong Kim, Joo-Han Kim Transactions of the Korean Society of Mechanical Engineers A.2012; 36(1): 37. CrossRef
Laser-assisted deposition of Cu bumps for microelectronic packaging Won-Seok CHOI, Joohan KIM Transactions of Nonferrous Metals Society of China.2012; 22: s683. CrossRef
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