Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Neuromorphic computing, inspired by the biological mechanisms of neural signal transmission, has emerged as a promising technology for efficient and parallel data processing with minimal power consumption. In this study, we developed floating-gate organic thin-film transistors (OTFTs) with self-assembled monolayer (SAM)-based tunneling layers to mimic the characteristics of artificial synapses. The tunneling layers were formed using mixed phosphonic acid SAMs with varying ratios of octadecylphosphonic acid (ODPA) and 12-pentafluorophenoxydodecylphosphonic acid (PFPA). The influence of these ratios on the memory and neuromorphic characteristics of the devices was systematically evaluated. Our results revealed that the ODPA ratio significantly impacts the hysteresis window, with higher ODPA content yielding improved memory characteristics. Conversely, the PFPA : ODPA ratio of 2:1 exhibited the lowest non-linearity (NL = 0.48), demonstrating the potential for highly accurate weight updates in neuromorphic devices. Additionally, pulse width modulation studies showed that a pulse width of 100 ms optimized the linearity and stability of long-term potentiation (LTP) and depression (LTD) characteristics. The combination of sol-gel processed AlOx as a floating-gate layer and tailored SAM-based tunneling layers allowed for precise control of device performance. These findings highlight the importance of molecular engineering in designing SAM layers to balance memory retention and neuromorphic functionality. This study provides a pathway for advancing organic floating-gate transistors as a core component in next-generation neuromorphic computing systems.

To enhance the tunneling electroresistance (TER) ratio of a ferroelectric tunnel junction (FTJ) device using Al-doped HfO₂ thin films, a thin insulating layer was prepared on a TiN bottom electrode, for which TiN was preliminarily treated at various temperatures in O₂ ambient. The composition and thickness of the inserted insulating layer were optimized at 600℃ and 50 Torr, and the FTJ showed a high TER ratio of 430. During the heat treatments, a titanium oxide layer formed on the surface of TiN, that suppressed oxygen vacancy generation in the ferroelectric thin film. It was found that the fabricated FTJ device exhibits two distinct resistance states with higher tunneling currents by properly heat-treating the TiN bottom electrode of the HfO₂-based FTJ devices in O₂ ambient.

The silicon dioxide (SiO2) was deposited using various gas as oxygen and nitrous oxide (N2O) in nowadays. In order to improve electrical characteristics and the interface state density (D_{it}) in low temperature, It was deposited with carbon dioxide (CO2) and silane (SiH4) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each D_{it} of SiO2 using CO2 and N2O gas was 1.30×1010 cm-2·eV-1 and 3.31×1010 cm-2·eV-1. It showed SiO2 using CO2 gas was about 2.55 times better than N2O gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using SiO2(CO2) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied SiO2(N2O) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show SiO2 using CO2 decrease the D_{it} and it improves the operating voltage.

Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin Al2O3 tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through Al2O3 layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant VBE between,0~1.2V, Ic has increased linearly with VCE forVCE＜VCE indicating the saturation region. As the VCE increases further, a plateau of Ic vs. VCE has appeared slightly at VCE-VBE, denoting forward-active region. With further increase of, has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.

Citations

• Device model for pixelless infrared image up-converters based on polycrystalline graphene heterostructures
  V. Ryzhii, M. S. Shur, M. Ryzhii, V. E. Karasik, T. Otsuji
  Journal of Applied Physics.2018;[Epub]     CrossRef

Citations

• Effects of Emission Layer Thickness on the Efficiency of Blue Phosphorescent Organic Light Emitting Diodes with Triple Layer Structure
  Yu Seok Seo, Dae Gyu Moon
  Journal of Korean Institute of Electrical and Electronic Materials Engineers.2010; 23(2): 143.     CrossRef