The increasing global demand for renewable energy has accelerated the deployment of offshore wind farms, thereby highlighting the need for advanced development and performance assessment techniques for dynamic submarine cables used in floating offshore wind systems. These cables are continuously subjected to combined thermal, electrical, and mechanical stresses, with mechanical loading playing a particularly dominant role. As a result, dynamic submarine cables exhibit degradation behaviors that differ significantly from those of conventional fixed submarine cables. This paper presents the design and implementation of a comprehensive evaluation system capable of applying combined thermal, electrical, and mechanical stresses to dynamic submarine cables. The system was validated using a 66 kV wet type submarine cable through commissioning tests and insulation performance measurements. Electrical stress of 72 kV, thermal stress exceeding 95°C, and mechanical stress corresponding to a bending radius of 20 times the cable diameter over 20 cycles were applied to verify system reliability. The subsequent insulation assessments quantitatively confirmed performance variations induced by the combined stresses. The results demonstrate that the proposed platform is the first system capable of simultaneously applying thermal, electrical, and mechanical stresses to dynamic submarine cables, and its operational performance has been successfully validated. This platform enables realistic reliability evaluation of dynamic cables used in floating offshore wind farms and is expected to improve the overall operational reliability of offshore wind power systems.

Multilayer ceramic capacitors (MLCCs) are essential for high-capacitance, miniaturized, and reliable electronic applications. This study examines the impact of layer stacking on the dielectric and electrical properties of MLCCs using a BaTiO₃-based dielectric with MgO, Mn₃O₄, Yb₂O₃, V₂O₅, and (BaCa)SiO₃ glass additives. MLCCs with 10 um-thick dielectric layers and varying Ni electrode layers (10, 30, 50, and 100 layers) were fabricated. The dielectric constant increases significantly up to 30 layers due to compressive stress and sintering densification but it becomes linear beyond 30 layers. Dissipation factor and ESR decrease with higher stacking due to improved sinterability, while breakdown voltage declines exponentially from defect accumulation and thermal stress. Insulation resistance decreases but stabilizes relative to capacitance. C-V results show stress-induced polarization suppression, which reduces the dielectric constant under high voltage. Optimized stacking and sintering conditions are crucial for MIL-PRF-32535 compliant MLCC designs.

This study investigates the insulation performance of a 66 kV dry-type submarine cable used in offshore wind farms under mechanical aging. During installation and operation, submarine cables are subjected to various mechanical stresses, including tension, compression, and bending, which can lead to insulation deterioration. In this study, XLPE samples extracted from a submarine cable were prepared and subjected to controlled tensile strain below the yield strain to evaluate their mechanical and electrical performance. Changes in tensile strength, elongation, and tan δ (dielectric loss factor) were measured to assess the extent of aging. The results indicate that as the applied strain and exposure duration increased, tensile strength and elongation decreased, while tan δ values increased, signifying a decline in electrical insulation performance. A strong negative correlation (R = -0.809) was observed between tan δ and tensile strength, demonstrating that mechanical aging significantly affects electrical properties. These findings highlight the importance of minimizing excessive mechanical stress during the installation and operation of submarine cables. The results provide valuable insights for enhancing the reliability of submarine cables in offshore wind farms and emphasize the necessity of optimized design and maintenance strategies to mitigate the effects of mechanical aging.

The increasing demand for renewable energy is driving the rapid expansion of the offshore wind industry, leading to intensified research on subsea cables. These cables endure combined thermal, electrical, and mechanical stresses, with mechanical stress being a critical failure factor. Environmental changes, such as seabed scouring, free spans, and seismic activity, accelerate cable degradation by introducing additional dynamic loads. Conventional monitoring systems primarily track thermal stress, lacking the ability to assess mechanical impacts. This study develops a system to simultaneously measure thermal and mechanical stress in subsea cables. Laboratory experiments confirm the system’s reliability, showing a temperature measurement error within 0.8% at 60℃ and a strain measurement error within 13% at 378 με. The proposed system aims to enhance failure prediction and maintenance strategies for offshore wind subsea cables.

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

The transfer characteristics of amorphous indium gallium zinc oxide thin film transistor (a-IGZO TFT) showed the distortion in the subthreshold region after gate bias stress, in addition to the parallel shift of threshold voltage. The capacitancevoltage (C-V) curve was also deformed from its initial shape after the gate bias stress. This study analyzes both the C-V and transfer curves plotted on the same gate voltage axis in order to investigate the mechanism driving the distortion in the transfer curve. It is deduced that an additional interfacial trap states at the bottom interface of a-IGZO are produced during gate bias stress, thereby they exhibit the back channel effect, which explains the origin of the distortion in the transfer curve and the deformation of C-V curve.

Using facing target magnetron sputtering (FTMS) with a graphite target source, carbon nitride thin films were deposited on silicon and glass substrates at different substrate temperatures to confirm the tribological, electrical, and structural properties of thin films. The substrate temperatures were room temperature, 150℃, and 300℃. The tribology and electrical properties of the carbon nitride thin films were measured as the substrate temperature increased, and a study on the relation between these results and structural properties was conducted. The results show that the increase in the substrate temperature during the fabrication of the carbon nitride thin films increased the hardness and elastic modulus values, the critical load value was increased, and the residual stress value was reduced. Moreover, the increase in the substrate temperature during thin-film deposition was attributed to the improvement in the electrical properties of carbon nitride thin film.

We studied the change of photovoltaic properties of a flexible CuIn_xGa(_1-x)Se₂ (CIGS) solar cell fabricated on polyimide by mechanical bending with curvature radii of 75 mm (75R) and 20 mm (20R). The flexible CIGS cells were flattened on a PET film, then placed and forced against the surface of a curved block fabricated with pre-designed curvatures. Both up (compressive) and down (tensile) bending were applied to a specimen of CIGS on PET with curvatures of 75R and 20R for 10,000 times and 2,000 times, respectively. From J-V measurements, we found that the conversion efficiency (Eff.) was reduced by 3% and 4% for up-and down-bending, respectively, at curvature 75R; it was greatly reduced by 15% for curvature 20R in the up-bending. However, the open circuit voltage (V_oc) and short-circuit current density (J_sc) seemed to change little, within 3%, for the applied mechanical stresses. The degradation in Eff. resulted from the deterioration of the series (R_s) and shunt (R_sh) resistances of the solar cell.

In this study, to develop angle ring pressboards for high voltage transformers, the radius and thickness are modified under the conditions of temperature and humidity. In particular, a pressboard with a thickness of 6 mm and a radius at the angled part were investigated based on the simulation of the principal stress from the angled optimization profile shape. As a result, by the appropriate application of a higher temperature, the solid insulation can be improved to reduce the moisture content for an optimized profile angle of a high voltage transformer. This also results in the improvement of the safety factor by 25%. It is determined that the electrical insulation properties of pressboards in high voltage transformers can be enhanced by improving their properties.

It was proven that the light outputs of blue GaN-based light-emitting diodes (LEDs) was seriously influenced by the application of external stress. We have simulated the wave function overlap of an electron and hole, which are significantly reduced by the development of stress. Consequently, its internal quantum efficiency decreased from 67.0% to 37.5%. To experimentally investigate the effect of stress, we designed and prepared a special zig system. By applying external tensile stress to compensate for the compressive stress innately developed in Blue LEDs, it was found that the optical output was greatly enhanced from 83.1 mcd to 117.2 mcd at a current of 100 mA, an increase of approximately 41%. In contrast, when the compressive stress is developed more by external compressive stress, we observed that the light output power was reduced from 89.0 mcd to 80.7 mcd, a decrease of approximately 9.3%.

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a SiO₂/Si₃N₄ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

We investigated the tribological properties of amorphous carbon (a-C) films deposited with CrC interlayers of various thicknesses as the adhesive layer. A-C and CrC thin films were deposited using the unbalanced magnetron (UBM) sputtering method with graphite and chromium as the targets. CrC films as the interlayer were fabricated under a-C films, and various structural, surface, and tribological properties of a-C films deposited with various CrC interlayer thicknesses were investigated. With various CrC interlayer thicknesses under a-C films, the tribological properties of CrC/a-C films were improved; the increased film thickness exhibited a maximum high hardness of over 27.5 GPa, high elastic modulus of over 242 GPa, critical load of 31 N, residual stress of 1.85 GPa, and a smooth surface below 0.09 nm at the condition of 30-nm CrC thickness.

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

Atomically thin MoS₂ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, MoS₂ single-crystal as a transistor channel after transfer onto a SiO2/Si substrate. The MoS2 FETs displayed n-channel characteristics with an electron mobility of 0.05 cm²/V-sec, and a current on/off ratio of ION/IOFF?5×10⁴. Application of bottom-gate voltage stresses, however, increased the interface charges on MoS2/SiO₂, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between 109 Å, 190 Å, 387 Å, and 818 Å which have the gate area 10-³ cm2. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

In this paper, semiconducting shield specimens for a DC cable is fabricated and characterized by measurement of volume resistance, tensile strength, and the coefficient of expansion to show the electrical and mechanical characteristics of the semiconducting shield. Due to the PTC phenomenon, the volume resistance at 25℃ increases rapidly in comparison to the volume resistance at 90℃. Since the compounding ratio of carbon black is low, the tensile strength and density become lower and the coefficient of expansion is increased. As the general specification of the tensile strength and density is 0.8 kgf/㎟ and 150%, respectively, the fabricated specimen in this paper has excellent mechanical characteristic.

In this paper, reliability of the two sandwiched MIM capacitors of Al2O3-HfO2-Al2O3 (AHA) and SiO2-HfO2-SiO2 (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/μm2 and 5.2 fF/μm2) over the entire frequency range and low leakage current density of ∼1 nA/cm2 at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (ΔC/C0) increases and the variation of voltage linearity (α/α0) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO (Nc-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (μFE) of Nc-embedded-IGZO TFT was 2.37 cm2/Vs and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (μFE of a-IGZO was 9.67 cm2/Vs and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (△V(TH)) of Nc-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during 10(5) s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.