In parallel with the efforts to improve the device performance in modern integrated circuits, it is necessary to downscale their core components, field-effect transistors (FETs), generally gauged by their physical gate length. Upon such device scaling, the emergence of the short-channel effect impedes further scaling into the nanometer scale in the silicon VLSI (Very-Large-Scale-Integration) system. To address this issue, two-dimensional (2D) semiconductors, leveraging their atomically thin thickness and dangling-bond-free characteristics, are being highlighted as a material solution for future scaling technology without severe mobility degradation. Despite the expected ideal physical properties, 2D semiconductors have yet to realize their full potential owing to the limited development of integration technology. In this context, we survey and review the tailored van der Waals integration technologies for 2D FETs. In particular, we provide an in-depth study of both van der Waals integrated contact and dielectric methods along with an explanation of customized materials. In essence, this van der Waals integrationcentered approach will be a core strategy to implement the high-performance 2D transistors that meet the demand of FET miniaturization.

Abstract: We have fabricated schottky barrier diode (SBDs) using polar (c-plane) and non polar (a-, m-plane) n-type 6H-SiC wafers. Ni/SiC ohmic contact was accomplished on the backside of the SiC wafers by thermal evaporation and annealed for 20minutes at 950℃ in mixture gas (N(2) 90% + H(2) balanced). The specific contact resistance was 3.6×10-4 Ω㎝2 after annealing at 950℃. The XRD results of the alloyed contact layer show that formation of NiSi2 layer might be responsible for the ohmic contact. The active rectifying electrode was formed by the same thermal evaporation of Ni thin film on topside of the SiC wafers and annealed for 5 minutes at 500℃ in mixture gas (N(2) 90% + H(2) balanced). The electrical properties of SBDs have been characterized by means of I-V and C-V curves. The forward voltage drop is about 0.95 V, 0.8 V and 0.8 V for c-, a- and m-plane SiC SBDs respectively. The ideality factor (η) of all SBDs have been calculated from log(I)-V plot. The values of ideality factor were 1.46, 1.46 and 1.61 for c-, a- and m-plane SiC SBDs, respectively. The schottky barrier height (SBH) of all SBDs have been calculated from C-V curve. The values of SBH were 1.37 eV, 1.09 eV and 1.02 eV for c-, a- and m-plane SiC SBDs, respectively.