Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Page Path

2
results for

"NVM"

Keywords

Publication year

Authors

"NVM"

Decrease of Interface Trap Density of Deposited Tunneling Layer Using CO2 Gas and Characteristics of Non-volatile Memory for Low Power Consumption
So Jin Lee, Kyung Soo Jang, Cam Phu Thi Nguyen, Tae Yong Kim, Jun Sin Yi
J Korean Inst Electr Electron Mater Eng 2016;29(7):394-399.   Published online July 1, 2016
DOI: https://doi.org/10.4313/JKEM.2016.29.7.394
The silicon dioxide (SiO2) was deposited using various gas as oxygen and nitrous oxide (N2O) in nowadays. In order to improve electrical characteristics and the interface state density (D_{it}) in low temperature, It was deposited with carbon dioxide (CO2) and silane (SiH4) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each D_{it} of SiO2 using CO2 and N2O gas was 1.30×1010 cm-2·eV-1 and 3.31×1010 cm-2·eV-1. It showed SiO2 using CO2 gas was about 2.55 times better than N2O gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using SiO2(CO2) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied SiO2(N2O) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show SiO2 using CO2 decrease the D_{it} and it improves the operating voltage.
  • 53 View
  • 0 Download
Unified Dual-Gate Phase Change RAM (PCRAM) with Phase Change Memory and Capacitor-Less DRAM
Joo Yeon Kim
J Korean Inst Electr Electron Mater Eng 2014;27(2):76-80.   Published online February 1, 2014
DOI: https://doi.org/10.4313/JKEM.2014.27.2.76
Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. VO2 changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with VO2. Current sensing margin of DRAM is 3 ㎂. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.
  • 52 View
  • 0 Download