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"NBIS"

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"NBIS"

Research Trends for Improvement of NBIS Instability in Amorphous In-Ga-ZnO Based Thin-Film Transistors
Geonju Yoon, Jinsu Park, Jaemin Kim, Jaehyun Cho, Sangwoo Bae, Jinseok Kim, Hyun-hoo Kim, Junsin Yi
J Korean Inst Electr Electron Mater Eng 2019;32(5):371-375.   Published online September 1, 2019
DOI: https://doi.org/10.4313/JKEM.2019.32.5.371
Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a SiO2/Si3N4 dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.
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Effect of SiO2 Buffer Layer Thickness on the Device Reliability of the Amorphous InGaZnO Pseudo-MOS Field Effect Transistor
Se Won Lee, Yeong Hyeon Hwang, Won Ju Cho
J Korean Inst Electr Electron Mater Eng 2012;25(1):24-28.   Published online January 1, 2012
DOI: https://doi.org/10.4313/JKEM.2012.25.1.24
In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO Ψ -MOSFET) with a stacked Si3N4/SiO2 (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a SiO2 buffer layer. The roles of a SiO2 buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and Si3N4. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick SiO2 buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin SiO2 buffer layer which highlighted bias and light-induced hole trapping into the Si3N4 layer. As a results, the pseudo-MOS transistor with a 20-nm-thick SiO2 buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(μFE) of 12.3 cm2/V·s, subthreshold slope (SS) of 148 mV/dec, trap density (Nt) of 4.52× 1011 cm-2, negative bias illumination stress (NBIS) ΔVth of 1.23 V, and negative bias temperature illumination stress (NBTIS) ΔVth of 2.06 V.
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