Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Page Path

1
results for

"Multi-level"

Keywords

Publication year

Authors

"Multi-level"

A Study on a Substrate-bias Assisted 2-step Pulse Programming for Realizing 4-bit SONOS Charge Trapping Flash Memory
Byung Cheul Kim, Chang Soo Kang, Hyun Yong Lee, Joo Yeon Kim
J Electr Electron Mater 2012;25(6):409-413.   Published online June 1, 2012
In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.
  • 12 View
  • 0 Download