In this study, we systematically investigated the effects of thermal atomic layer deposition (ALD) conditions on the electrical characteristics of conductive-filament-based volatile threshold switching memristors with a Pt/Al₂O₃/Ag structure. Although volatile threshold switching memristors have attracted significant attention for neuromorphic computing applications such as spiking neural networks, the impact of dielectric deposition conditions on their switching behavior remains relatively unexplored. The number of ALD cycles was varied from 40 to 200, and the deposition temperature was varied from 50 to 250°C to evaluate their effects on threshold voltage (V_th), off-state resistance (R_off), and device yield. Devices fabricated using 75–150 ALD cycles showed clear volatile threshold switching behavior with relatively high device yield, whereas excessively low or high cycle numbers resulted in short-type and open-type failures, respectively. In addition, V_th and R_off tended to increase at higher deposition temperatures, while the device yield significantly degraded above 150°C. These results indicate that the number of ALD cycles and the deposition temperature define a critical process window for achieving volatile threshold switching while suppressing both short-type and open-type failures. This study provides practical guidelines for optimizing dielectric ALD conditions in conductive-filament-based volatile threshold switching memristors for future neuromorphic hardware applications.

n-type silicon shows the better tolerance towards metal impurities with a higher minority carrier lifetime compared to p-type silicon substrate. Due to better lifetime stability as compared to p-type during illumination made the photovoltaic community to switch toward n-type wafers for high efficiency silicon solar cells. We fabricated the front electrode of the n-type solar cell with AgAl paste. The electrodes characteristics of the AgAl paste depend on the contact junction depth that is closely related to the firing temperature. Metal contact depth with p+ emitter, with optimized depth is important as it influence the resistance. In this study, we optimize the firing condition for the effective formation of the metal depth by varying the firing condition. The firing was carried out at temperatures below 670℃ with low contact depth and high contact resistance. It was noted that the contact resistance was reduced with the increase of firing temperature. The contact resistance of 5.99 mΩ㎠ was shown for the optimum firing temperature of 865℃. Over 900℃, contact junction is bonded to the Si through the emitter, resulting the contact resistance to shunt. we obtained photovoltaic parameter such as fill factor of 76.68%, short-circuit current of 40.2 mA/cm2, open-circuit voltage of 620 mV and convert efficiency of 19.11%.

As packing density in integrated circuits increases, multilevel metallization process has beenwidely used. But hillock formed in the bottom layers of aluminum are well known to make interlayershort in multilevel metallization. In this study, the effects of ion implantation to the metal film anddeposition temperature on the hillock formation were investigated. The Al-1%Si thin film of 1 ㎛thickness was DC sputtered with substrate (SiO2/Si) temperature of 20℃, 200℃, and 400℃, respectively. Ar ions (1×1015 cm-2: 150 keV) and B ions (1×1015 cm-2, 30 keV, 150 keV) were implanted to the Al-Sithin film. The deposited films were evaluated by SEM, surface profiler and resistance measuring system. As a results, Ar implanting to Al-Si film is very effective to reduce hillock size in the metal depositiontemperature below than 200℃, and B implanting to an Al-Si film is effective to reduce hillock density inthe high temperature deposition conditions around 400℃. Line width less than 3 ㎛ was free of hillockafter alloying.

Resistance of the front electrode is the highest proportion of the ingredients of the series resistance in crystalline silicon solar cell. While resistance of the front electrode is decreased with larger area, it induces the optical loss, causing the conversion efficiency drop. Therefore the front electrode with high aspect ratio increasing its height and decreasing is necessary for high-efficiency solar cell in considering shadowing loss and resistance of front electrode. In this paper, we used the screen printing method to form high aspect ratio electrode by multiple printing. Screen printing is the straightforward technology to establish the electrodes in silicon solar cell fabrication. The several printed front electrodes with Ag paste on silicon wafer showed the significantly increased height and slightly widen finger. As a result, the resistance of the front electrode was decreased with multiple printing even if it slightly increased the shadowing loss. We showed the improved electrical characteristics for c-Si solar cell with repeatedly printed front electrode by 0.5%. It lays a foundation for high efficiency solar cell with high aspect ratio electrode using screen printing.

Citations

• Study on Improving Uniformity of Ag Printed Electric Line through Vacuum Annealing and Resulting Reduction in Heat Generation and High-Temperature Environmental Durability
  Sung Jun Park, Gun Woong Kim, Jaebum Jeong, Jin Hong Park, Jun Young Kim
  Journal of the Korean Solar Energy Society.2024; 44(6): 145.     CrossRef