Organic solar cells based on bulk heterojunction (BHJ) structures have attracted considerable attention because of their low fabrication cost, mechanical flexibility, and compatibility with solution-processing techniques. In BHJ organic photovoltaic devices, nanoscale morphology and crystallinity of the photoactive layer critically influence photovoltaic performance. In this study, the effects of solvent selection and thermal annealing on crystallization evolution and photovoltaic characteristics of P3HT:PCBM organic solar cells were systematically investigated. Three different solvents, including toluene, chlorobenzene (CB), and dichlorobenzene (DCB), were employed for active-layer fabrication, followed by post-thermal annealing treatment. UV–visible absorption spectroscopy revealed solvent-dependent differences in molecular ordering and intermolecular π–π interactions within the active layer. X-ray diffraction analysis confirmed that thermal annealing significantly enhanced crystallinity and lamellar ordering of P3HT domains, particularly for CB-processed films. Electrical characterization demonstrated that solvent evaporation behavior strongly affects photovoltaic performance. Among the investigated devices, the thermally annealed CB-processed device exhibited the highest power conversion efficiency of 1.83% with an enhanced short-circuit current density of 7.057 mA cm⁻². The improved device performance is attributed to optimized crystallization behavior and balanced nanoscale phase separation induced by the moderate evaporation characteristics of CB. In contrast, although DCB-assisted films exhibited relatively strong optical absorption and enhanced crystallinity, excessively slow solvent evaporation likely induced excessive aggregation and coarse phase separation, limiting efficient photovoltaic characteristics. These results demonstrate that solvent engineering combined with thermal annealing is an effective strategy for controlling morphology evolution and crystallization behavior in P3HT:PCBM bulk heterojunction solar cells.

GaN nanowire (NW)-based hybrid structures have attracted attention for optoelectronic applications due to their high surface area and efficient carrier transport. However, the optical transparency of GaN NWs is often limited by unintended residual species accumulated on the surface and in the inter-wire regions, as well as defect-related absorption, leading to reduced light transmission. In this work, we demonstrate that thermal annealing significantly improves the optical transparency of GaN NWs grown on indium tin oxide (ITO)/glass substrates. The transmittance increased from 47.9% to 78.5% at 550 nm after rapid thermal annealing at 800^oC for 3 min, while a comparable value (~75.5%) was achieved at 600^oC for 5 min. PbBr₃ was deposited onto the GaN NWs to form hybrid structures, and temperature-dependent photoluminescence (TDPL) measurements revealed enhanced emission stability with suppressed peak shift and reduced spectral broadening. Arrhenius analysis based on a two-channel model revealed that the activation energy of the dominant non-radiative recombination pathway increased from 62 meV in the as-grown sample to 85 meV after thermal annealing, while its relative contribution remained nearly unchanged. In contrast, the shallow trap-assisted pathway exhibited a similar activation energy of approximately 6 meV in both samples, but its contribution decreased from 0.35 to 0.17 after annealing. As a result, the internal quantum efficiency (IQE) improved from 75.9% to 87.4%. These results show that thermal annealing improves optical transparency by removing residuals and suppresses defect-related recombination, leading to enhanced carrier dynamics and improved optical performance of PbBr₃-based hybrid structures.

e investigated the effects of post-annealing in vacuum, nitrogen, and hydrogen atmospheres on the structural, electrical, and optical properties of 600 nm thick Al-doped ZnO (ZnO:Al) thin films deposited by RF magnetron sputtering at room temperature. Post-annealing in hydrogen atmosphere at 400℃ for 1 hour showed the most significant improvement in electrical properties. Resistivity decreased from 9.11×10⁻³ to 1.4×10⁻³ Ω·cm, electron mobility increased from 4.11 to 18.23 cm²/V·s, and electron carrier concentration increased from 1.63×10²⁰ to 4.85×10²⁰ cm⁻³. In contrast, post-annealing in vacuum and nitrogen atmospheres resulted in degraded electrical properties due to oxygen and nitrogen chemisorption at grain boundaries. The enhancement in hydrogen-annealed films was attributed to the formation of additional oxygen vacancies and desorption of adsorbed oxygen species from grain boundaries. All films maintained excellent optical transparency of 80-90% in the visible range. The optical bandgap exhibited a blue-shift from 3.365 eV to 3.624 eV due to the Burstein-Moss effect induced by the increased electron carrier concentration. These results confirmed that hydrogen atmosphere post-annealing is the most effective method for enhancing the electrical conductivity of ZnO:Al thin films while maintaining high optical transparency.

In this study, Y₂O₃ thin films were deposited on Si(100) wafers using an RF sputtering system with a Y₂O₃ target. The Y₂O₃ thin film was confirmed to have a thickness of 227 nm/min and a uniformity of 1.34% at a substrate temperature of 400℃. All samples were annealed at 600, 800, and 1,000℃ for 1 hour in an O₂ gas atmosphere using the furnace. The analysis of the XRD patterns revealed that the peak intensity increased with annealing up to 800℃, but decreased when the annealing temperature was raised to 1,000℃. The XPS analysis confirmed the onset of crystallization at 800℃, in agreement with the trends observed in the XRD results. According to the AFM results, the surface became slightly smoother after heat treatment, as indicated by a reduced RMS roughness of approximately 1.792 nm.

With the advancement of the information society, the demand for highly integrated and multi-functional electronic devices is rapidly increasing. To meet these demands, high-performance transistors with low power consumption, high-speed operating, and mechanical flexibility are essential. Among various candidates, semiconducting single-walled carbon nanotubes (s-SWCNT)-based transistors, which exhibit intrinsically ambipolar characteristics, have emerged as promising components for CMOS-like circuits. In this study, s-SWCNT were selectively dispersed using rr-P3DDT, a thiophene-based conjugated polymer, and filed-effect transistors (FETs) were fabricated by inducting directional alignment for enhanced charge transport through an off-centered spin-coating process. The electrical characteristics of the fabricated s-SWCNT FETs were evaluated under various thermal annealing conditions (100℃, 150℃, 200℃, and 250℃). Off-centered spin-coated and high temperature annealed s- SWCNT FETs exhibited high field-effect mobilities over 5 cm²/Vs in both p-type and n-type operation, along with ideal Vshaped ambipolar transfer curves. These results indicate a significant enhancement in ambipolar performance due to efficient desorption of residual oxygen and water molecules in active channel via high temperature annealing. Furthermore, CMOS-like inverter circuits demonstrated an ideal inversion voltage (VIN = V_DD/2) and a high voltage gain of approximately 9.5. These findings highlight the potential of SWCNT-based materials for realizing next-generation flexible electronic circuits that combine high-performance, energy efficiency, and simplified solution-processing.

Recently, oxide semiconductors have assumed a pivotal role in electronic displays and transparent electronic devices such as amorphous indium gallium zinc oxide (a-IGZO), characterized by high electron mobility and excellent stability. a- IGZO is very suitable for next-generation applications such as flexible displays because it is possible to manufacture highperformance transistors even at low temperatures. However, since the electrical properties tend to deteriorate in hightemperature environments, research aimed at improving thermal stability is needed. In this study, a low-temperature plasma annealing process was introduced to improve the high-temperature stability of the a-IGZO thin film. This process enhances electron mobility by reducing defects in the a-IGZO film and provides stable device performance even under high-temperature conditions. As a result of the experiments of 5 min, 10 min, 15 min, and 20 min, the a-IGZO TFT, which was subjected to plasma annealing at 160℃ for 5 min, showed the best electrical performance, especially in charge mobility and current-voltage characteristics. The technical potential for improving the performance of a-IGZO-based display device was emphasized, and the foundation for applying this power generation to flexible displays and next-generation electronic devices was laid. Future research will focus on determining the optimal annealing conditions by exploring various temperature ranges and plasma parameters to integrate these results into the actual device manufacturing process. These efforts are expected advance significantly to advancing next-generation high-performance display technology.

The solution-based fabrication process for resistive random-access memory (ReRAM) offers several advantages over conventional vapor deposition processes, including simplicity, cost-effectiveness, and high versatility for coating complex structures over large areas. In this study, a TiO₂-based ReRAM device was fabricated using a solution process with Pt top and P⁺⁺-Si bottom electrodes. The synthesized TiO₂ films contain a residual Cl element as revealed by X-ray photoelectron spectroscopy (XPS). Reversible volatile resistance switching was observed due to the formation of conductive Ti-O-Ti networks in the TiO₂ layer. Post-annealing led to an increase in the threshold voltage (Vth). Asymmetric Current-Voltage characteristics was observed due to the different in the work functions of the electrodes. Additionally, the influence of compliance current settings on filament formation and hysteresis behavior was systematically investigated. The results demonstrated that higher compliance currents enhanced the hysteresis width for both positive and negative voltage bias conditions.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.

The display industry has recently been at the forefront of innovative advancements in modern electronic devices. Technological progress such as flexible display holds significant potential across various application fields, particularly in wearable devices and rollable displays. A low-temperature process is essential for fabricating such displays. One of the key technologies in displays is the thin film transistor (TFT), with amorphous indium gallium zinc oxide (a-IGZO) receiving particular attention. a-IGZO is widely applied in high-performance displays due to its high charge mobility and stability. While a thermal treatment above 350℃ is typically required to maximize the electrical performance of a-IGZO TFTs, such high temperatures pose challenges for utilizing polymer substrates like plastics. Here, we thesis investigates the simultaneous lowtemperature plasma annealing process to develop next-generation high-performance flexible display devices. To define the optimal temperature, devices were fabricated and analyzed at varying temperatures of 40℃, 80℃, 120℃, and 160℃. Experimental results indicated that devices fabricated at 160℃ and 80℃ exhibited superior performance, with those at 160℃ demonstrating better performance in terms of current ratio, threshold voltage, and subthreshold swing. These findings confirm that the simultaneous low-temperature plasma annealing process is effective for next-generation high-performance displays.

Memristors, as next-generation memory devices, have garnered significant academic interest. Among them, TiO₂/TiO_2-x based memristors have particularly attracted substantial scholarly attention. Research on the activation and stability of TiO2 based memristor devices through process parameters is essential. Here, to determine the impact of process parameters on the activation of TiO₂/TiO_2-x based memristor devices, we fabricated the memristor devices using a sputtering system andconducted annealing at 400℃. Additionally, to analyze the electrical characteristics of the devices, we measured the I-V curves and C-V curves. Also, we examined TiO₂/TiO_2-x based memristor devices surface using SEM. Consequently, it was observed that the devices subjected to annealing exhibited improved hysteresis curves in the I-V characteristics, a reduced bandgap, and changes in resistance compared to the non-annealed devices. The retention test results further demonstrated that the set/reset characteristics of the devices were stable, confirming their potential applicability as memory devices.

The transparent electrode characteristics of the SnO₂/AgNi/SnO₂ (OMO) multilayer structures prepared by sputtering were investigated according to the annealing temperature. Ni-doped Ag of various compositions was selected as the metal layer and heat treatment was performed at 100~300℃ to evaluate the thermal stability of the metals. The manufactured OMO multilayer structures were heat treated for 6 hours at 400~600℃ in an N₂ atmosphere. The structural, electrical, and optical properties of the OMO structures before and after annealing were evaluated and analyzed using a UV-VIS spectrophotometer, 4-point probe, XPS, FE-SEM, etc. OMO with Ni-doped Ag shows improved performance due to the reduction of structural defects of Ag during annealing, but OMO structure with pure Ag shows degradation characteristics due to Ag diffusion into the oxide layer during high-temperature annealing. The figure of merit (FOM) of SnO₂/Ag/SnO₂ was highest at room temperature and gradually decreased as the heat treatment temperature increased. On the other hand, the FOM value of SnO₂/AgNi/SnO₂ mostly showed its maximum value at high temperature(~550℃). In particular, the FOM value of SnO₂/Ag-Ni (3.2 at%)/SnO₂ was estimated to be approximately 2.38×10^-2 Ω^-1. Compared to transparent electrodes made of other similar materials, the FOM value of the SnO₂/Ag-Ni (3.2 at%)/SnO₂ multilayer structure is competitive and is expected to be used as an alternative transparent conductive electrode in various devices.

This study investigates the post-thermal treatment effects on the efficiency of silicon heterojunction solar cells, specifically examining the influence of annealing on p-type microcrystalline silicon oxide and ITO thin films. By assessing changes in carrier concentration, mobility, resistivity, transmittance, and optical bandgap, we identified conditions that optimize these properties. Results reveal that appropriate annealing significantly enhances the fill factor and current density, leading to a notable improvement in overall solar cell efficiency. This research advances our understanding of thermal processing in siliconbased photovoltaics and provides valuable insights into the optimization of production techniques to maximize the performance of solar cells.

The polymer crystallization process, promoting the formation of ferroelectric β-phase, is essential for developing polyvinylidene fluoride (PVDF)-based high-performance piezoelectric energy harvesters. However, traditional high-temperature annealing is unsuitable for the manufacture of flexible piezoelectric devices due to the thermal damage to plastic components that occurs during the long processing times. In this study, we investigated the feasibility of introducing a flash lamp annealing that can rapidly induce the β-phase in the PVDF layer while avoiding device damage through selective heating. The flash lightirradiated PVDF films achieved a maximum β-phase content of 76.52% under an applied voltage of 300 V and an on-time of 1.5 ms, a higher fraction than that obtained through thermal annealing. The PVDF-based piezoelectric energy harvester with the optimized irradiation condition generates a stable output voltage of 0.23 V and a current of 102 nA under repeated bendings. These results demonstrate that flash lamp annealing can be an effective process for realizing the mass production of PVDF-based flexible electronics.

In this study, ITO thin films were fabricated on a glass substrate at different thicknesses without introducing oxygen using RF sputtering system. The structural, electrical, and optical properties were evaluated at various thicknesses ranging from 50 to 300 mm. As the thickness of deposited ITO thin film become thicker from 50 to 100 mm, carrier concentration, mobility, and band gap energy also increased while the resistivity and transmittance decreased in the visible light region. When the film thickness increased from 100 to 300 mm, the carrier concentration, mobility, and band gap energy decreased while the resistivity and transmittance increased. The optimum electrical properties were obtained for the ITO film 100 nm. After optimizing the thickness, the ITO thin films were post-annealed at different temperatures ranging from 100 to 300℃. As the annealing temperature increased, the ITO crystal phase became clearer and the grain size also increased. In particular, the ITO thin film annealed at 300℃ indicated high carrier concentration (4.32 × 10²¹ cm^-3), mobility (9.01 cm2/V·s) and low resistivity (6.22 × 10^-4 Ω·cm). This means that the optimal post-annealing temperature is 300℃ and this ITO thin film is suitable for use in solar cells and display application.

As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher chip density, thin-film layers have been deposited iteratively. The poor film uniformity resulting from deposition or chemical mechanical planarization (CMP) significantly affects chip yield. Therefore, the development of novel fabrication processes to enhance film uniformity is required. In this context, high-pressure deuterium annealing (HPDA) is proposed to reduce the surface roughness resulting from the CMP. The HPDA is carried out in a diluted deuterium atmosphere to achieve cost-effectiveness while maintaining high pressure. To confirm the effectiveness of HPDA, time-of-flight secondary-ion mass spectrometry (ToF-SIMS) and atomic force microscopy (AFM) are employed. It is confirmed that the absorbed deuterium gas facilitates the diffusion of silicon atoms, thereby reducing surface roughness.

Laser-induced plasmonic sintering of metal nanoparticles (NPs) holds significant promise as a technology for producing flexible conducting electrodes. This method offers immediate, straightforward, and scalable manufacturing approaches, eliminating the need for expensive facilities and intricate processes. Nevertheless, the metal NPs come at a high cost due to the intricate synthesis procedures required to ensure long-term reliability in terms of chemical stability and the prevention of NP aggregation. Herein, we induced the self-generation of metal nanoparticles from Ag organometallic ink, and fabricated highly conductive electrodes on flexible substrates through laser-assisted plasmonic annealing. To demonstrate the practicality of the fabricated flexible electrode, it was configured in a mesh pattern, realizing multi-touchable flexible touch screen panel.

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

The effects of the annealing temperature on the structural, morphological, and luminescent properties of SrWO₄:Sm³⁺ thin films grown on quartz substrates by radio-frequency magnetron sputtering were investigated. The thin films were annealed at various annealing temperatures for 20 min in a rapid thermal annealer after growing the thin films. The experimental results showed that the annealing temperature has a significant effect on the properties of the SrWO₄:Sm³⁺ thin films. The crystal structure of the as-grown SrWO₄:Sm³⁺ thin films was transformed from amorphous to crystalline after annealing at 800℃. The preferred orientation along (112) plane and a significant increase in average grain size by 820 nm were observed with increasing the annealing temperature. The average optical transmittance in the wavelength range of 500~1,100 nm was decreased from 72.0% at 800℃ to 44.2% at an annealing temperature of 1,000℃, where the highest value in the photoluminescence intensity was obtained. In addition to the red-shift of absorption edge, a higher annealing temperature caused the optical band gap energy of the SrWO₄:Sm³⁺ thin films to fall rapidly. These results suggest that the structural, morphological, and luminescent properties of SrWO4:Sm3+ thin films can be controlled by varying annealing temperature.

The Ga₂O₃ thin films were deposited using an RF sputtering system and the effect of crystallographic and optical properties under rapid thermal annealing conditions on Ga₂O₃ thin film was evaluated. A rapid thermal annealing method can fabricate a crystalline Ga₂O₃ thin film which is applied to various fields with a low cost and a high efficiency compared with the conventional post-annealing method. In this study, the Ga₂O₃ treated at 900℃ for 1 min showed the beta and gamma phases in XRD measurement. In optical properties, the crystalline Ga₂O₃ represented a high transmittance of more than 80% in the visible region and was calculated with a high optical bandgap energy of 4.58 eV. The beta and gamma phases Ga₂O₃ can be obtained by adjusting the rapid thermal annealing temperatures, and the various properties such as the optical bandgap energy can be controlled. Moreover, it is expected that crystalline Ga₂O₃ can be applied to various devices by controlling not only temperature but process time.

Flash lamp annealing (FLA) of metal nanoparticle (NP) ink has provided powerful strategies to fabricate highperformance electrodes on a flexible substrate because of its rapid processing capability (in milliseconds), low-temperature process, and compatibility with to roll-to-roll process. However, metal NPs [e.g., gold (Au), silver (Ag), copper (Cu), etc.] have limitations such as difficulty in synthesizing fine metal NPs (diameter less than 10 nm), high price, and degradation during ink storage and FLA processing. In this regard, organometallic ink has been proposed as a material that can replace metal NPs due to their low-cost (usually 1/100 times cheaper than metal nano inks), low-temperature processability, and high material stability. Despite these advantages, the fabrication of flexible electrodes through FLA treatment of organometallic compounds has not been extensively researched. In this paper, we experimentally guide how to determine the optimal conditions for forming electrodes on flexible substrates by considering material parameters, and flashlight processing parameters (energy density, pulse duration, etc) to minimize the difficulties that may arise during the FLA of organometallic ink.

Perovskite materials are promising candidates for next-generation optoelectronic devices owing to their outstanding external quantum efficiency, high color purity, and ability to tune the light emission wavelength. However, conventional thermal annealing processes caused the degradation of perovskite, resulting in poor optoelectronic properties and a short lifetime. Herein, we propose a laser-induced recrystallization of perovskite thin film to enhance its light-emitting properties. Laser-induced recrystallization process was performed using rapid and instantaneous laser heating, which successfully induced grain growth of the perovskite material. The laser processing conditions were thoroughly optimized based on theoretical calculations and various material analyses such as x-ray diffraction, scanning electron microscope, and photoluminescence spectroscopy.

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

The ferroelectricity in Hf_0.5Zr_0.5O₂ (HZO) thin films is one of the most interesting topics for next-generation nonvolatile memory applications. It is known that a crystallization process is required at a temperature of 400℃ or higher to form an orthorhombic phase that results in the ferroelectric properties of the HZO film. However, to realize the integration of ferroelectric HZO films in the back-end-of-line, it is necessary to reduce the annealing temperature below 400℃. This study aims to comprehensively analyze the ferroelectric properties according to the annealing temperature (350-500℃) and time (1-5 h) using a furnace as a crystallization method for HZO films. As a result, the ferroelectric behaviors of the HZO films were achieved at a temperature of 400℃ or higher regardless of the annealing time. At the annealing temperature of 350℃, the ferroelectric properties appeared only when the annealing time was sufficiently increased (4 h or more). Based on these results, it was experimentally confirmed that the optimization of the annealing temperature and time is very important for the ferroelectric phase crystallization of HZO films and the improvement of their ferroelectric properties.

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

We investigated the effect of a post-annealing process using ultraviolet (UV) light on the electrical properties of solution-processed InZnO (IZO) thin-film transistors (TFTs). UV light was irradiated on IZO TFTs for different time periods of 0s, 30s, and 90s. We measured transfer and retention stability curves to evaluate the performance of the fabricated TFTs. In addition, we measured height, amplitude, and phase AFM images to analyze changes in the surface and morphology of the devices. AFM measurements were performed by setting the drive amplitude of the cantilever tip to 47.9 mV in tapping mode, then dividing the device surface into 500 nm × 500 nm. In the case of IZO TFT irradiated with UV for 30s, the electron mobility and Ion/Ioff ratio were improved, the threshold voltage was reduced by approximately 2 V, and the subthreshold swing also decreased form 1.34 V/dec to 1.11 V/dec.

Ga₂O₃/n-type 4H-SiC heterojunction diodes were fabricated by RF magnetron sputtering. The optical properties of Ga₂O₃ and electrical properties of diodes were investigated. I-V characteristics were compared with simulation data from the Atlas software. The band gap of Ga₂O₃ was changed from 5.01 eV to 4.88 eV through oxygen annealing. The doping concentration of Ga₂O₃ was extracted from C-V characteristics. The annealed oxygen exhibited twice higher doping concentration. The annealed diodes showed improved turn-on voltage (0.99 V) and lower leakage current (3 pA). Furthermore, the oxygen-annealed diodes exhibited a temperature cross-point when temperature increased, and its ideality factor was lower than that of as-grown diodes.

We prepared yarned carbon nanotube (CNT) fibers from a CNT forest synthesized on a Si wafer by chemical vapor deposition (CVD). The yarned CNT fibers were thermally annealed to reduce their resistance by removing the amorphous carbonaceous impurities present in the fibers. The resistance of the yarned CNT fiber gradually decreased with an increase in the annealing temperature from 200℃ to 400℃ but increased again above 450℃. We carried out thermogravimetric analysis (TGA) to confirm the burning properties of the amorphous carbonaceous impurities and the crystalline CNTs present in the fibers. The pattern of the mass change of the sample CNT fibers was very similar to that of the resistance change. We conclude that CNT fibers should be thermally annealed at temperatures below 400℃ for reducing and stabilizing their resistance.

In this work, we have investigated the effect of a 30-min thermal anneal at 550℃ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.