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교류형 플라즈마 디스플레이에서 낮은 주사 전압에 의한 배경광을 낮추기 위한 새로운 구동 파형

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New Driving Waveform to Reduce Background Light by Low Scan Voltage in AC Plasma Display Panel

Byung-gwon Cho
J Electr Electron Mater 2025;38(3):290-295.
Published online: May 1, 2025
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The characteristics of each address discharge were investigated when the voltages of the scan and common electrodes were lowered simultaneously during an address period under the same address voltage conditions in an AC plasma display panel. It was confirmed that the delay time of address discharge shortened as the voltage decreased. However, the background light increased because the low scanning voltage generated more discharge between the electrodes of the upper and lower plates in the reset period. To lower the background light, a positive voltage was applied to the address electrode of the lower panel during the period when the rising ramp wave was applied, and a floating voltage was applied to the address electrode during the period when the falling ramp wave was applied during the reset period. As a result, the background light could be lowered by about 30%.

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New Driving Waveform to Reduce Background Light by Low Scan Voltage in AC Plasma Display Panel
J Electr Electron Mater. 2025;38(3):290-295.   Published online May 1, 2025
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

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Include:
New Driving Waveform to Reduce Background Light by Low Scan Voltage in AC Plasma Display Panel
J Electr Electron Mater. 2025;38(3):290-295.   Published online May 1, 2025
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