Electrostatic discharge has been considered as a major reliability problem in the semiconductorindustry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PADmust be designed with a protection circuitry that creates a low impedance discharge path for ESDcurrent. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuitwith latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD(bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuitis measured. In the result, the proposed ESD protection circuit has latch-up immunity and highrobustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristiccan be applied to analog integrated circuits.
