In this work, the effect of sputtering working pressure for the tellurium film and its thin-film transistor was investigated. The transfer characteristics of tellurium thin-film transistors were improved by increasing the working pressure during sputtering process. As increasing working pressure, physical and optical properties of Te films such as crystallinity, transmittance, and surface roughness were improved. Therefore, the improved transfer characteristics of Te thin-film transistors may originate from both improved interface properties between the silicon oxide gate dielectric layer and the tellurium active layer with an improved quality of Te film. In conclusion, the control of working pressure during sputtering would be important for obtaining highperformance tellurium-based thin film transistor.

We investigated the effect of a post-annealing process using ultraviolet (UV) light on the electrical properties of solution-processed InZnO (IZO) thin-film transistors (TFTs). UV light was irradiated on IZO TFTs for different time periods of 0s, 30s, and 90s. We measured transfer and retention stability curves to evaluate the performance of the fabricated TFTs. In addition, we measured height, amplitude, and phase AFM images to analyze changes in the surface and morphology of the devices. AFM measurements were performed by setting the drive amplitude of the cantilever tip to 47.9 mV in tapping mode, then dividing the device surface into 500 nm × 500 nm. In the case of IZO TFT irradiated with UV for 30s, the electron mobility and Ion/Ioff ratio were improved, the threshold voltage was reduced by approximately 2 V, and the subthreshold swing also decreased form 1.34 V/dec to 1.11 V/dec.

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a SiO₂/Si₃N₄ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

A soft baking process was used to enhance the electrical characteristics of solution-processed indium-zincoxide (IZO) thin-film transistors (TFTs). We demonstrate a stable soft baking process using a hot plate in air to maintain the electrical stability and improve the electrical performance of IZO TFTs. These oxide transistors exhibited good electrical performance; a field-effect mobility of 7.9 cm²/Vs, threshold voltage of 1.4 V, sub-threshold slope of 0.5 V/dec, and a current on/off ratio of 2.9×10⁷ were measured. To investigate the static response of our solutionprocessed IZO TFTs, simple resistor load type inverters were fabricated by connecting a resistor (5 or 10 MΩ). Our IZO TFTs, which were manufactured using the soft baking process at a baking temperature of 120℃, performed well at the operating voltage, and are therefore a good candidate for use in advanced logic circuits and transparent display backplanes.

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of 3.0(±0.2) cm²/Vs, high Ion/Ioff ratio of 1.1×10⁷, threshold voltage of 0.4(±0.1) V, and subthreshold swing of 0.7(±0.01) V/dec. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

We report on thin-film transistors based on TiO_x pre-annealed by femtosecond laser pulses. A 30-nm thick TiO_x active channel layer was initially deposited by an ALD system. The TiO_x semiconducting films were annealed by irradiation with a femtosecond laser (power: 3 W/cm²) for 5, 25, and 50s. Atomic force microscopy images revealed that the surface of a TiO_x film without femtosecond laser pre-annealing was relatively rough, while after annealing with femtosecond laser pulses, the surface of the TiO_x films became smooth. With increasing radiation time, the surrounding gas atmosphere could have a larger impact on the TiO_x surface; meanwhile, the thin-film roughness decreased. Thin-film transistors with TiO_x active channels pre-annealed at 50s exhibited good transfer characteristics and an on-to-off current ratio of ~10³.

In this study, we examine the electrical properties of diketopyrrolopyrrole (DPP) containing polymer semiconductors that have been reported to show high performance with ambipolar characteristics. We prepared three different DPP based polymer semiconductors (PDPPTPT, PDPP3T, and PDPP2T-TT) and fabricated organic thin film transistors (OTFTs) with ambipolar polymer semiconductors as an active layer. All three DPP polymers showed only p-type properties at initial measurements. However, after annealing in vacuum oven for 24 hours, it was found that the DPP based polymers have both p-type and n-type properties. It is speculated that the residual impurities supposedly regarded as a strong electron trap source were eliminated during the vacuum process.

Threshold voltage shift has been observed from many thin-film transistors (TFTs) and the time evolution of the shift can be modeled as the stretched-exponential and -hyperbola function. These analytic models are derived from the kinetic equation for defect-creation or charge-trapping and the equation consists of only reversible reactions. In reality TFT``s a shift is permanent due to an irreversible reaction and, as a result, it is reasonable to consider that both reversible and irreversible reactions exist in a TFT. In this paper the case when both reactions exist in parallel and make a combined threshold voltage shift is modeled and simulated. The results show that a combined threshold voltage shift observed from a TFT may agrees with the analytic models and, thus, the analytic models don``t guarantee whether the cause of the shift is defection-creation or charge-trapping.

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

In this study, the effects of soft baking temperature on the solution derived ZTO (Zn-Sn-O) TFTs (thin-film transistors) as a In-free oxide semiconductor were investigated. In spite of the same hard baking at high temperature(600℃), the electrical properties of ZTO TFT was greatly changed by a small difference in soft baking temperature(180~250℃). The performance of TFT was deteriorated as the soft baking temperature increased. Therefore, it is important to remove the water-related defects well as organic impurities from the ZTO films during soft baking for fabrication of solution-derived high performance of TFTs.

In this paper, TiO2 based thin-film transistors (TFTs) were fabricated using by an atomic layer deposition with high aspect ratio and excellent step coverage. Ti02 semiconducting layer was deposited showing a rutile phase through the rapid thermal annealing process, and exhibited TFT characteristics with a 200 pm channel length of low-leakage currents (none of current flow during off-state), stable threshold voltages (-10 V - 0 V), and a much higher on/off current ratio (