Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Page Path

1
results for

"Tin Layer"

Keywords

Publication year

Authors

"Tin Layer"

Regular Paper : Method of Solving Oxidation Problem in Copper Pillar Bump Packaging Technology of High Density IC
One Chul Jung, Sang Jeen Hong, Dae Wha Soh, Jae Ryong Hwang, Il Hwan Cho
J Electr Electron Mater 2010;23(12):919-923.   Published online December 1, 2010
Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have 100μm pitch were introduced with fabrication process using a KM-1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with 330℃ and 500 N thermo-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.
  • 10 View
  • 0 Download