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"SHJ solar cell"

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"SHJ solar cell"

Effect on the Thermal Treatment for Improving Efficiency in Silicon Heterojunction Solar Cells
Hyeong Gi Park, Junsin Yi
J Electr Electron Mater 2024;37(4):439-444.   Published online July 1, 2024
DOI: https://doi.org/10.4313/JKEM.2024.37.4.12
This study investigates the post-thermal treatment effects on the efficiency of silicon heterojunction solar cells, specifically examining the influence of annealing on p-type microcrystalline silicon oxide and ITO thin films. By assessing changes in carrier concentration, mobility, resistivity, transmittance, and optical bandgap, we identified conditions that optimize these properties. Results reveal that appropriate annealing significantly enhances the fill factor and current density, leading to a notable improvement in overall solar cell efficiency. This research advances our understanding of thermal processing in siliconbased photovoltaics and provides valuable insights into the optimization of production techniques to maximize the performance of solar cells.
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A Study on Improved Open-Circuit Voltage Characteristics Through Bi-Layer Structure in Heterojunction Solar Cells
Hongrae Kim, Sungjin Jeong, Jaewoong Cho, Sungheon Kim, Seungyong Han, Suresh Kumar Dhungel, Junsin Yi
J Electr Electron Mater 2022;35(6):603-609.   Published online November 1, 2022
DOI: https://doi.org/10.4313/JKEM.2022.35.6.9
Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a- Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I1) and the next one a-SiOx:H(I2) were used, where a-SiOx:H(I2) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I1). Using a-SiOx:H as I2 layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiOx:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiOx:H microstructure can help the carrier transportation through tunneling and thermal emission.
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