Skip to main navigation Skip to main content
  • KIEEME

J Electr Electron Mater : Journal of Electrical and Electronic Materials

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS

Page Path

1
results for

"Pd interlayer"

Keywords

Publication year

Authors

"Pd interlayer"

Improvement of Thermal Stability of Ni-InGaAs Using Pd Interlayer for n-InGaAs MOSFETs
Meng Li, Geonho Shin, Jeongchan Lee, Jungwoo Oh, Hi-deok Lee
J Electr Electron Mater 2018;31(3):141-145.   Published online March 1, 2018
Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at 570℃ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above 500℃. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.
  • 6 View
  • 0 Download