In this study, we systematically investigated the effects of thermal atomic layer deposition (ALD) conditions on the electrical characteristics of conductive-filament-based volatile threshold switching memristors with a Pt/Al₂O₃/Ag structure. Although volatile threshold switching memristors have attracted significant attention for neuromorphic computing applications such as spiking neural networks, the impact of dielectric deposition conditions on their switching behavior remains relatively unexplored. The number of ALD cycles was varied from 40 to 200, and the deposition temperature was varied from 50 to 250°C to evaluate their effects on threshold voltage (V_th), off-state resistance (R_off), and device yield. Devices fabricated using 75–150 ALD cycles showed clear volatile threshold switching behavior with relatively high device yield, whereas excessively low or high cycle numbers resulted in short-type and open-type failures, respectively. In addition, V_th and R_off tended to increase at higher deposition temperatures, while the device yield significantly degraded above 150°C. These results indicate that the number of ALD cycles and the deposition temperature define a critical process window for achieving volatile threshold switching while suppressing both short-type and open-type failures. This study provides practical guidelines for optimizing dielectric ALD conditions in conductive-filament-based volatile threshold switching memristors for future neuromorphic hardware applications.

Aggressive device scaling has severely degraded the switching characteristics of CMOS transistors. This issue has led to the development of tunneling FETs (TFETs) as an alternative. TFETs, with their asymmetric doping of the source and drain regions, offer improved subthreshold swing (SS) compared to conventional MOSFETs. However, despite this advantage, TFETs still suffer from ambipolar current, which increases off-state current (IOFF). This paper introduces an approach to applying hetero gate dielectrics (HGDs) in nanosheet (NS) TFETs to reduce ambipolar current characteristics. The magnitude of the drain electric field is reduced by selectively forming a high-k dielectric near the source region This configuration allows the TFETs to avoid unintended band-to-band tunneling (BTBT) and suppress ambipolar current during the off-state.

Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μ_n) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.