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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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"InZnO"

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"InZnO"

Properties of Indium Zinc Oxide Thin Films Prepared by Pulsed Laser Deposition
Hak Soon Choi, Il Kyo Jeong, Mun Soo Shin, Heon Oh Kim, Yong Soo Kim
J Electr Electron Mater 2011;24(7):537-542.   Published online July 1, 2011
Recently, n-InZnO/p-CuO oxide diode has attracted great attention due to possible application for selector device of 3-dimensional cross-point resistive memory structures. To investigate the detailed properties of InZnO (IZO), we have deposited IZO films on the fused quartz substrate using PLD (pulsed laser deposition) method at oxygen pressure of 1∼100 mTorr and substrate temperature of RT∼600℃. The influence of oxygen pressure and substrate temperature on structural, optical and electrical of IZO films is analyzed using XRD (x-ray diffraction), SEM (scanning electron microscopy), UV-Vis spectrophotometry, spectroscopic ellipsometry (SE) and hall measurements. The XRD results shows that the deposited thin films are polycrystalline over 300℃ of substrate temperature independent of oxygen pressure. The resistivity of films was increased as oxygen pressure and substrate temperature decrease. The thickness and optical constants of the deposited films measured with UV-Vis spectrophotometer were also compared with those of broken SEM and SE results.
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Study on the Electrical Characteristics of Solution-processed ZrInZnO Thin-film Transistors
Tae Hoon Jeong, Si Joon Kim, Doo Hyun Yoon, Woong Hee Jeong, Dong Lim Kim, Hyun Soo Lim, Hyun Jae Kim
J Electr Electron Mater 2011;24(6):458-462.   Published online June 1, 2011
Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 cm2/Vs, the threshold voltage (Vth) of 2.1 V, the on/off ratio of 4.95×10(6), and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are temporarily trapped in the gate insulator, the semiconductor, or the interface between both layers.
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