In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga’s figure of merit (~94.22 MW/cm²) than the symmetric structure (~46.93 MW/cm²), and the breakdown voltage of the device increases by approximately 70%.

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.