Post-metallization annealing (PMA) has been employed in silicon-based CMOS fabrication to enhance MOSFET reliability and performance. However, although deuterium annealing can reduce interface traps between the Si and SiO₂ gate dielectric, it remains insufficient to fully passivate these traps. In this context, a multiple PMA process, including additional hydrogen annealing, is proposed to further reduce dangling bonds. Silicon-based MOSFETs are fabricated to verify the proposed annealing process architecture. Electrical characterization of the threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and carrier mobility (μn) is conducted to investigate the impact of the multiple PMA. This study provides a guideline for PMA in MOSFET fabrication, with improvements in both performance and reliability.
As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher chip density, thin-film layers have been deposited iteratively. The poor film uniformity resulting from deposition or chemical mechanical planarization (CMP) significantly affects chip yield. Therefore, the development of novel fabrication processes to enhance film uniformity is required. In this context, high-pressure deuterium annealing (HPDA) is proposed to reduce the surface roughness resulting from the CMP. The HPDA is carried out in a diluted deuterium atmosphere to achieve cost-effectiveness while maintaining high pressure. To confirm the effectiveness of HPDA, time-of-flight secondary-ion mass spectrometry (ToF-SIMS) and atomic force microscopy (AFM) are employed. It is confirmed that the absorbed deuterium gas facilitates the diffusion of silicon atoms, thereby reducing surface roughness.
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Analysis of Yield and Electrical Characteristics of Ag Electrode-Based Volatile Threshold Switching Memristors with Al2O3 Dielectric Films Under Different ALD Process Conditions Wan-Sik Woo, Seung-Jin Lee, Moon-Seok Kim, Seung-Bae Jeon Journal of Electrical and Electronic Materials.2026; 39(5): 493. CrossRef
The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using hightemperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), and off-state current (IOFF). Moreover, the LTDA is perfectly compatible with CMOS processes.
High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (VTH), subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage (IG) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO2 interfaces as well as eliminate the bulk trap in SiO2. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.
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