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J Electr Electron Mater : Journal of Electrical and Electronic Materials

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"DAHC"

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"DAHC"

Regular Paper : Analysis of Reliability for Different Device Type in 65 nm CMOS Technology
Chang Su Kim, Sung Kyu Kwon, Jae Nam Yu, Sun Ho Oh, Seong Yong Jang, Hi Deok Lee
J Korean Inst Electr Electron Mater Eng 2014;27(12):792-796.   Published online December 1, 2014
DOI: https://doi.org/10.4313/JKEM.2014.27.12.792
In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond 0.18 μm CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.
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Dependence of Device Performance and Reliability on Chanel Direction in PMOSFET`s
Jung Deuk Bok, Ye Ji Park, In Shik Han, Hyuk Min Kwon, Byoung Seok Park, Sang Uk Park, Min Gyu Lim, Yi Sun Chung, Jung Hwan Lee, Hi Deok Lee
J Korean Inst Electr Electron Mater Eng 2010;23(6):431-435.   Published online June 1, 2010
DOI: https://doi.org/10.4313/JKEM.2010.23.6.431
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